| /drivers/net/ethernet/mellanox/mlx5/core/esw/ |
| A D | legacy.c | 148 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port); in esw_create_legacy_fdb_table() 271 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_UPLINK); in _mlx5_eswitch_set_vepa_locked() 274 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); in _mlx5_eswitch_set_vepa_locked()
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| /drivers/net/ethernet/mellanox/mlx5/core/ |
| A D | eswitch_offloads_termtbl.c | 207 misc_parameters.source_port); in mlx5_eswitch_offload_is_uplink_port() 209 misc_parameters.source_port); in mlx5_eswitch_offload_is_uplink_port()
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| A D | eswitch_offloads.c | 157 MLX5_SET(fte_match_set_misc, misc, source_port, vport); in mlx5_eswitch_set_rule_source_port() 165 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); in mlx5_eswitch_set_rule_source_port() 978 MLX5_SET(fte_match_set_misc, misc, source_port, vport); in mlx5_eswitch_add_send_to_vport_rule() 985 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); in mlx5_eswitch_add_send_to_vport_rule() 1151 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); in peer_miss_rules_setup() 1178 MLX5_SET(fte_match_set_misc, misc, source_port, vport); in esw_set_peer_miss_rule_source_port() 1486 misc_parameters.source_port); in mlx5_esw_set_flow_group_source_port() 2128 MLX5_SET(fte_match_set_misc, misc, source_port, vport); in mlx5_esw_set_spec_source_port() 2131 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); in mlx5_esw_set_spec_source_port() 2718 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); in __esw_set_master_egress_rule() [all …]
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| A D | eswitch.c | 243 MLX5_SET(fte_match_set_misc, mv_misc, source_port, MLX5_VPORT_UPLINK); in __esw_fdb_set_vport_rule() 244 MLX5_SET_TO_ONES(fte_match_set_misc, mc_misc, source_port); in __esw_fdb_set_vport_rule()
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| /drivers/net/ethernet/mellanox/mlx5/core/diag/ |
| A D | fs_tracepoint.c | 172 PRINT_MASKED_VAL_MISC(u16, source_port, source_port, p, "%u"); in print_misc_parameters_hdrs()
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| /drivers/net/ethernet/mellanox/mlx5/core/steering/hws/ |
| A D | definer.c | 501 u16 source_port = HWS_GET_MATCH_PARAM(match_param, misc_parameters.source_port); in hws_definer_set_source_port_gvmi() local 505 ret = mlx5hws_vport_get_gvmi(peer_ctx, source_port, &vport_gvmi); in hws_definer_set_source_port_gvmi() 508 mlx5hws_err(fc->ctx, "Vport 0x%x is disabled or invalid\n", source_port); in hws_definer_set_source_port_gvmi() 852 outer_headers.tcp_sport, eth_l4_outer.source_port); in hws_definer_conv_outer() 856 outer_headers.udp_sport, eth_l4_outer.source_port); in hws_definer_conv_outer() 1028 inner_headers.tcp_sport, eth_l4_inner.source_port); in hws_definer_conv_inner() 1032 inner_headers.udp_sport, eth_l4_inner.source_port); in hws_definer_conv_inner() 1256 if (HWS_GET_MATCH_PARAM(match_param, misc_parameters.source_port)) { in hws_definer_conv_misc()
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| A D | definer.h | 366 u8 source_port[0x10]; member
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| A D | bwc_complex.c | 386 HWS_CLEAR_MATCH_PARAM(mask, misc_parameters.source_port); in hws_bwc_matcher_complex_params_clear_fld()
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| /drivers/net/ethernet/intel/ice/ |
| A D | ice_protocol_type.h | 420 __be16 source_port; member
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| /drivers/net/ethernet/mellanox/mlx5/core/steering/sws/ |
| A D | dr_ste_v0.c | 856 DR_STE_SET_TAG(eth_l3_ipv4_5_tuple, tag, source_port, spec, tcp_sport); in dr_ste_v0_build_eth_l3_ipv4_5_tuple_tag() 857 DR_STE_SET_TAG(eth_l3_ipv4_5_tuple, tag, source_port, spec, udp_sport); in dr_ste_v0_build_eth_l3_ipv4_5_tuple_tag() 1641 DR_STE_SET_ONES(src_gvmi_qp, bit_mask, source_gvmi, misc_mask, source_port); in dr_ste_v0_build_src_gvmi_qpn_bit_mask() 1680 misc->source_port); in dr_ste_v0_build_src_gvmi_qpn_tag() 1683 misc->source_port); in dr_ste_v0_build_src_gvmi_qpn_tag() 1690 misc->source_port = 0; in dr_ste_v0_build_src_gvmi_qpn_tag()
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| A D | dr_matcher.c | 315 return (misc->source_sqn || misc->source_port); in dr_mask_is_gvmi_or_qpn_set() 451 rx && mask.misc.source_port) { in dr_matcher_set_ste_builders() 452 mask.misc.source_port = 0; in dr_matcher_set_ste_builders()
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| A D | dr_ste.c | 722 if (mask->misc.source_port && mask->misc.source_port != 0xffff) { in mlx5dr_ste_build_pre_check() 814 spec->source_port = IFC_GET_CLR(fte_match_set_misc, mask, source_port, clr); in dr_ste_copy_mask_misc()
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| A D | dr_rule.c | 1095 if (mask->misc.source_port) { in dr_rule_skip() 1096 if (rx && value->misc.source_port != MLX5_VPORT_UPLINK) in dr_rule_skip() 1099 if (!rx && value->misc.source_port == MLX5_VPORT_UPLINK) in dr_rule_skip()
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| A D | dr_ste_v1.c | 1094 DR_STE_SET_TAG(eth_l3_ipv4_5_tuple_v1, tag, source_port, spec, tcp_sport); in dr_ste_v1_build_eth_l3_ipv4_5_tuple_tag() 1095 DR_STE_SET_TAG(eth_l3_ipv4_5_tuple_v1, tag, source_port, spec, udp_sport); in dr_ste_v1_build_eth_l3_ipv4_5_tuple_tag() 1836 DR_STE_SET_ONES(src_gvmi_qp_v1, bit_mask, source_gvmi, misc_mask, source_port); in dr_ste_v1_build_src_gvmi_qpn_bit_mask() 1873 vport_cap = mlx5dr_domain_get_vport_cap(vport_dmn, misc->source_port); in dr_ste_v1_build_src_gvmi_qpn_tag() 1876 misc->source_port); in dr_ste_v1_build_src_gvmi_qpn_tag() 1883 misc->source_port = 0; in dr_ste_v1_build_src_gvmi_qpn_tag()
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| A D | mlx5_ifc_dr_ste_v1.h | 295 u8 source_port[0x10]; member
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| A D | mlx5_ifc_dr.h | 243 u8 source_port[0x10]; member
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| A D | dr_types.h | 645 u32 source_port:16; member
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| /drivers/net/ |
| A D | amt.c | 598 &tunnel->ip4, ntohs(tunnel->source_port), in __amt_update_relay_status() 1105 tunnel->source_port, in amt_send_multicast_data() 1164 tunnel->source_port, in amt_send_membership_query() 2700 tunnel->source_port = udph->source; in amt_request_handler() 2722 (__force u32)tunnel->source_port, in amt_request_handler()
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| /drivers/infiniband/hw/mlx5/ |
| A D | fs.c | 1498 MLX5_SET(fte_match_set_misc, misc, source_port, rep->vport); in mlx5_ib_set_rule_source_port() 1503 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); in mlx5_ib_set_rule_source_port()
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