| /drivers/gpu/drm/xe/ |
| A D | xe_gt_sriov_pf_config.c | 403 spare = gt->sriov.pf.spare.ggtt_size; in pf_get_spare_ggtt()
675 return max_hole > spare ? max_hole - spare : 0; in pf_get_max_ggtt()
742 spare = gt->sriov.pf.spare.num_ctxs; in pf_get_spare_ctxs()
756 if (spare && spare < pf_get_min_spare_ctxs(gt)) in pf_set_spare_ctxs()
759 gt->sriov.pf.spare.num_ctxs = spare; in pf_set_spare_ctxs()
1044 spare = gt->sriov.pf.spare.num_dbs; in pf_get_spare_dbs()
1058 if (spare && spare < pf_get_min_spare_dbs(gt)) in pf_set_spare_dbs()
1061 gt->sriov.pf.spare.num_dbs = spare; in pf_set_spare_dbs()
1298 spare = gt->sriov.pf.spare.lmem_size; in pf_get_spare_lmem()
1618 avail = free > spare ? free - spare : 0; in pf_query_max_lmem()
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| A D | xe_guc_db_mgr.c | 115 unsigned int count, unsigned int spare) in dbm_reserve_chunk_locked() argument
128 if (spare) { in dbm_reserve_chunk_locked()
130 if (used + count + spare > dbm->count) in dbm_reserve_chunk_locked()
200 unsigned int count, unsigned int spare) in xe_guc_db_mgr_reserve_range() argument
205 ret = dbm_reserve_chunk_locked(dbm, count, spare); in xe_guc_db_mgr_reserve_range()
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| A D | xe_gt_sriov_pf_types.h | 62 struct xe_gt_sriov_spare_config spare; member
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| A D | xe_guc_db_mgr.h | 17 int xe_guc_db_mgr_reserve_range(struct xe_guc_db_mgr *dbm, unsigned int count, unsigned int spare);
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| A D | xe_ggtt.c | 840 u64 xe_ggtt_largest_hole(struct xe_ggtt *ggtt, u64 alignment, u64 *spare) in xe_ggtt_largest_hole() argument
857 if (spare) in xe_ggtt_largest_hole()
858 *spare -= min3(*spare, hole_size, max_hole); in xe_ggtt_largest_hole()
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| A D | xe_ggtt.h | 38 u64 xe_ggtt_largest_hole(struct xe_ggtt *ggtt, u64 alignment, u64 *spare);
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| /drivers/soc/tegra/fuse/ |
| A D | fuse-tegra30.c | 107 .spare = 0x144,
123 .spare = 0x180,
279 .spare = 0x200,
450 .spare = 0x280,
508 .spare = 0x280,
601 .spare = 0x280,
671 .spare = 0x280,
692 .spare = 0xcf0,
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| A D | fuse.h | 23 unsigned int spare; member
74 u32 __init tegra_fuse_read_spare(unsigned int spare);
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| A D | fuse-tegra.c | 334 u32 __init tegra_fuse_read_spare(unsigned int spare) in tegra_fuse_read_spare() argument
336 unsigned int offset = fuse->soc->info->spare + spare * 4; in tegra_fuse_read_spare()
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| /drivers/mtd/nand/raw/ |
| A D | mtk_nand.c | 323 u32 fmt, spare, i; in mtk_nfc_hw_runtime_config() local
328 spare = mtk_nand->spare_per_sector; in mtk_nfc_hw_runtime_config()
365 spare >>= 1; in mtk_nfc_hw_runtime_config()
368 if (nfc->caps->spare_size[i] == spare) in mtk_nfc_hw_runtime_config()
1211 if (*sps >= spare[i] && spare[i] >= spare[closest_spare]) { in mtk_nfc_set_spare_per_sector()
1213 if (*sps == spare[i]) in mtk_nfc_set_spare_per_sector()
1218 *sps = spare[closest_spare]; in mtk_nfc_set_spare_per_sector()
1232 u32 spare; in mtk_nfc_ecc_init() local
1270 free = spare - free; in mtk_nfc_ecc_init()
1278 spare -= NFI_FDM_MAX_SIZE; in mtk_nfc_ecc_init()
[all …]
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| A D | marvell_nand.c | 954 u8 *spare, int spare_len, in marvell_nfc_check_empty_chunk() argument
968 if (!spare) in marvell_nfc_check_empty_chunk()
974 spare, spare_len, chip->ecc.strength); in marvell_nfc_check_empty_chunk()
1364 marvell_nfc_xfer_data_in_pio(nfc, spare, in marvell_nfc_hw_ecc_bch_read_chunk()
1366 spare += FIFO_DEPTH * BCH_SEQ_READS; in marvell_nfc_hw_ecc_bch_read_chunk()
1377 u8 *data = buf, *spare = chip->oob_poi; in marvell_nfc_hw_ecc_bch_read_page() local
1403 spare, spare_len, page); in marvell_nfc_hw_ecc_bch_read_page()
1409 spare += spare_len; in marvell_nfc_hw_ecc_bch_read_page()
1635 const u8 *spare = chip->oob_poi; in marvell_nfc_hw_ecc_bch_write_page() local
1656 spare, spare_len, page); in marvell_nfc_hw_ecc_bch_write_page()
[all …]
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| A D | lpc32xx_slc.c | 405 static void lpc32xx_slc_ecc_copy(uint8_t *spare, const uint32_t *ecc, int count) in lpc32xx_slc_ecc_copy() argument
412 spare[i + 2] = (uint8_t)(ce & 0xFF); in lpc32xx_slc_ecc_copy()
414 spare[i + 1] = (uint8_t)(ce & 0xFF); in lpc32xx_slc_ecc_copy()
416 spare[i] = (uint8_t)(ce & 0xFF); in lpc32xx_slc_ecc_copy()
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| /drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| A D | smu11_driver_if_vangogh.h | 150 uint8_t spare[2]; member
173 uint16_t spare; member
202 uint16_t spare; member
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| A D | smu13_driver_if_v13_0_5.h | 91 uint16_t spare; member
124 uint8_t spare[3]; member
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| A D | smu12_driver_if.h | 130 uint8_t spare[2]; member
198 uint16_t spare; member
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| A D | smu13_driver_if_yellow_carp.h | 136 uint8_t spare[3]; member
164 uint16_t spare; member
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| A D | smu13_driver_if_v13_0_4.h | 137 uint8_t spare[3]; member
165 uint16_t spare; //[centi] member
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| A D | smu14_driver_if_v14_0_0.h | 142 uint8_t spare[2]; member
222 uint32_t spare[6]; member
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| A D | dcn31_smu.h | 145 uint8_t spare[3]; member
173 uint16_t spare; member
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| /drivers/s390/char/ |
| A D | sclp_diag.h | 53 u8 spare; member
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| /drivers/firmware/qcom/ |
| A D | qcom_scm.c | 891 int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) in qcom_scm_restore_sec_cfg() argument
898 .args[1] = spare, in qcom_scm_restore_sec_cfg()
936 int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) in qcom_scm_iommu_secure_ptbl_size() argument
942 .args[0] = spare, in qcom_scm_iommu_secure_ptbl_size()
957 int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) in qcom_scm_iommu_secure_ptbl_init() argument
966 .args[2] = spare, in qcom_scm_iommu_secure_ptbl_init()
981 int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size) in qcom_scm_iommu_set_cp_pool_size() argument
988 .args[1] = spare, in qcom_scm_iommu_set_cp_pool_size()
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| /drivers/gpu/drm/amd/pm/powerplay/inc/ |
| A D | smu74.h | 227 uint8_t spare; member
473 uint8_t spare[2]; member
807 uint32_t spare; member
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| A D | smu8_fusion.h | 37 uint8_t spare[3]; member
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| A D | dcn314_smu.h | 64 uint8_t spare[3]; member
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| A D | dcn315_smu.h | 83 uint8_t spare[3]; member
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