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Searched refs:src_offset (Results 1 – 25 of 64) sorted by relevance

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/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_2/
A Dia_css_sdis2.host.c201 unsigned int src_offset = 0, dst_offset = 0; in ia_css_translate_dvs2_statistics() local
238 &htemp_ptr[0 * table_size + src_offset], size_bytes); in ia_css_translate_dvs2_statistics()
240 &htemp_ptr[1 * table_size + src_offset], size_bytes); in ia_css_translate_dvs2_statistics()
242 &htemp_ptr[2 * table_size + src_offset], size_bytes); in ia_css_translate_dvs2_statistics()
244 &htemp_ptr[3 * table_size + src_offset], size_bytes); in ia_css_translate_dvs2_statistics()
248 &vtemp_ptr[0 * table_size + src_offset], size_bytes); in ia_css_translate_dvs2_statistics()
250 &vtemp_ptr[1 * table_size + src_offset], size_bytes); in ia_css_translate_dvs2_statistics()
252 &vtemp_ptr[2 * table_size + src_offset], size_bytes); in ia_css_translate_dvs2_statistics()
254 &vtemp_ptr[3 * table_size + src_offset], size_bytes); in ia_css_translate_dvs2_statistics()
256 src_offset += table_width; /* aligned table width */ in ia_css_translate_dvs2_statistics()
/drivers/gpu/drm/nouveau/
A Dnouveau_bo85b5.c45 u64 src_offset = mem->vma[0].addr; in nva3_bo_move_copy() local
58 PUSH_NVSQ(push, NV85B5, 0x030c, upper_32_bits(src_offset), in nva3_bo_move_copy()
59 0x0310, lower_32_bits(src_offset), in nva3_bo_move_copy()
69 src_offset += (PAGE_SIZE * line_count); in nva3_bo_move_copy()
A Dnouveau_bo90b5.c38 u64 src_offset = mem->vma[0].addr; in nvc0_bo_move_copy() local
51 PUSH_NVSQ(push, NV90B5, 0x030c, upper_32_bits(src_offset), in nvc0_bo_move_copy()
52 0x0310, lower_32_bits(src_offset), in nvc0_bo_move_copy()
62 src_offset += (PAGE_SIZE * line_count); in nvc0_bo_move_copy()
A Dnouveau_bo9039.c43 u64 src_offset = mem->vma[0].addr; in nvc0_bo_move_m2mf() local
62 NVVAL(NV9039, OFFSET_IN_UPPER, VALUE, upper_32_bits(src_offset)), in nvc0_bo_move_m2mf()
64 OFFSET_IN, lower_32_bits(src_offset), in nvc0_bo_move_m2mf()
79 src_offset += (PAGE_SIZE * line_count); in nvc0_bo_move_m2mf()
A Dnouveau_bo5039.c45 u64 src_offset = mem->vma[0].addr; in nv50_bo_move_m2mf() local
107 NVVAL(NV5039, OFFSET_IN_UPPER, VALUE, upper_32_bits(src_offset)), in nv50_bo_move_m2mf()
112 PUSH_MTHD(push, NV5039, OFFSET_IN, lower_32_bits(src_offset), in nv50_bo_move_m2mf()
129 src_offset += amount; in nv50_bo_move_m2mf()
A Dnouveau_bo0039.c52 u32 src_offset = old_reg->start << PAGE_SHIFT; in nv04_bo_move_m2mf() local
73 PUSH_MTHD(push, NV039, OFFSET_IN, src_offset, in nv04_bo_move_m2mf()
89 src_offset += (PAGE_SIZE * line_count); in nv04_bo_move_m2mf()
/drivers/gpu/drm/radeon/
A Drv770_dma.c43 uint64_t src_offset, uint64_t dst_offset, in rv770_copy_dma() argument
76 radeon_ring_write(ring, src_offset & 0xfffffffc); in rv770_copy_dma()
78 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in rv770_copy_dma()
79 src_offset += cur_size_in_dw * 4; in rv770_copy_dma()
A Devergreen_dma.c107 uint64_t src_offset, in evergreen_copy_dma() argument
141 radeon_ring_write(ring, src_offset & 0xfffffffc); in evergreen_copy_dma()
143 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in evergreen_copy_dma()
144 src_offset += cur_size_in_dw * 4; in evergreen_copy_dma()
A Devergreen_cs.c2894 u64 src_offset, dst_offset, dst2_offset; in evergreen_dma_cs_parse() local
2959 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2984 src_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2985 src_offset <<= 8; in evergreen_dma_cs_parse()
2994 src_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
3018 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3064 src_offset = radeon_get_ib_value(p, idx+3); in evergreen_dma_cs_parse()
3104 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3166 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3196 src_offset <<= 8; in evergreen_dma_cs_parse()
[all …]
A Dsi_dma.c231 uint64_t src_offset, uint64_t dst_offset, in si_copy_dma() argument
264 radeon_ring_write(ring, lower_32_bits(src_offset)); in si_copy_dma()
266 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in si_copy_dma()
267 src_offset += cur_size_in_bytes; in si_copy_dma()
A Dr600_dma.c444 uint64_t src_offset, uint64_t dst_offset, in r600_copy_dma() argument
477 radeon_ring_write(ring, src_offset & 0xfffffffc); in r600_copy_dma()
479 (upper_32_bits(src_offset) & 0xff))); in r600_copy_dma()
480 src_offset += cur_size_in_dw * 4; in r600_copy_dma()
A Dradeon_asic.h86 uint64_t src_offset,
157 uint64_t src_offset,
348 uint64_t src_offset, uint64_t dst_offset,
352 uint64_t src_offset, uint64_t dst_offset,
472 uint64_t src_offset, uint64_t dst_offset,
546 uint64_t src_offset, uint64_t dst_offset,
725 uint64_t src_offset, uint64_t dst_offset,
796 uint64_t src_offset, uint64_t dst_offset,
800 uint64_t src_offset, uint64_t dst_offset,
A Dr200.c84 uint64_t src_offset, in r200_copy_dma() argument
114 radeon_ring_write(ring, src_offset); in r200_copy_dma()
117 src_offset += cur_size; in r200_copy_dma()
A Dr600_cs.c2383 u64 src_offset, dst_offset; in r600_dma_cs_parse() local
2441 src_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2442 src_offset <<= 8; in r600_dma_cs_parse()
2451 src_offset = radeon_get_ib_value(p, idx+5); in r600_dma_cs_parse()
2452 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; in r600_dma_cs_parse()
2463 src_offset = radeon_get_ib_value(p, idx+2); in r600_dma_cs_parse()
2464 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in r600_dma_cs_parse()
2474 src_offset = radeon_get_ib_value(p, idx+2); in r600_dma_cs_parse()
2475 src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in r600_dma_cs_parse()
2486 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in r600_dma_cs_parse()
[all …]
A Dcik_sdma.c579 uint64_t src_offset, uint64_t dst_offset, in cik_copy_dma() argument
613 radeon_ring_write(ring, lower_32_bits(src_offset)); in cik_copy_dma()
614 radeon_ring_write(ring, upper_32_bits(src_offset)); in cik_copy_dma()
617 src_offset += cur_size_in_bytes; in cik_copy_dma()
/drivers/gpu/drm/vmwgfx/
A Dvmwgfx_blit.c361 u32 src_offset, in vmw_bo_cpu_blit_line() argument
369 u32 src_page = src_offset >> PAGE_SHIFT; in vmw_bo_cpu_blit_line()
371 u32 src_page_offset = src_offset & ~PAGE_MASK; in vmw_bo_cpu_blit_line()
419 src_offset += copy_size; in vmw_bo_cpu_blit_line()
458 u32 src_offset, u32 src_stride, in vmw_external_bo_copy() argument
487 vsrc += src_offset; in vmw_external_bo_copy()
491 src_size -= src_offset; in vmw_external_bo_copy()
544 u32 src_offset, u32 src_stride, in vmw_bo_cpu_blit() argument
585 vmw_src, src_offset, src_stride, in vmw_bo_cpu_blit()
626 ret = vmw_bo_cpu_blit_line(&d, dst_offset, src_offset, w); in vmw_bo_cpu_blit()
[all …]
/drivers/gpu/drm/vc4/
A Dvc4_validate.c493 uint32_t src_offset = 0; in vc4_validate_bin_cl() local
498 while (src_offset < len) { in vc4_validate_bin_cl()
500 void *src_pkt = unvalidated + src_offset; in vc4_validate_bin_cl()
506 src_offset, cmd); in vc4_validate_bin_cl()
513 src_offset, cmd); in vc4_validate_bin_cl()
517 if (src_offset + info->len > len) { in vc4_validate_bin_cl()
520 src_offset, cmd, info->name, info->len, in vc4_validate_bin_cl()
521 src_offset + len); in vc4_validate_bin_cl()
532 src_offset, cmd, info->name); in vc4_validate_bin_cl()
536 src_offset += info->len; in vc4_validate_bin_cl()
[all …]
/drivers/gpu/drm/i915/gt/
A Dintel_migrate.c566 *cs++ = src_offset; in emit_copy_ccs()
601 *cs++ = src_offset; in emit_copy()
612 *cs++ = src_offset; in emit_copy()
621 *cs++ = src_offset; in emit_copy()
692 u32 src_offset, dst_offset; in intel_context_migrate_copy() local
739 src_offset = 0; in intel_context_migrate_copy()
742 src_offset = 0; in intel_context_migrate_copy()
745 src_offset = CHUNK_SZ; in intel_context_migrate_copy()
782 src_offset, src_sz); in intel_context_migrate_copy()
834 src_offset, src_access, len); in intel_context_migrate_copy()
[all …]
/drivers/gpu/drm/qxl/
A Dqxl_ioctl.c76 int src_offset; member
92 info->src_offset); in apply_reloc()
239 reloc_info[i].src_offset = reloc.src_offset; in qxl_process_single_command()
242 reloc_info[i].src_offset = 0; in qxl_process_single_command()
/drivers/gpu/drm/xe/
A Dxe_map.h33 size_t src_offset, size_t len) in xe_map_memcpy_from() argument
36 iosys_map_memcpy_from(dst, src, src_offset, len); in xe_map_memcpy_from()
/drivers/usb/isp1760/
A Disp1760-hcd.c327 src = src_base + (bank_addr | src_offset); in bank_reads8()
329 if (src_offset < PAYLOAD_OFFSET) { in bank_reads8()
351 if (src_offset < PAYLOAD_OFFSET) in bank_reads8()
371 isp1760_reg_write(priv->regs, ISP176x_HC_MEMORY, src_offset); in isp1760_mem_read()
374 bank_reads8(priv->base, src_offset, ISP_BANK_0, dst, bytes); in isp1760_mem_read()
411 return isp1760_mem_read(hcd, src_offset, (u16 *)dst, bytes); in mem_read()
413 isp1763_mem_read(hcd, (u16)src_offset, (u16 *)dst, bytes); in mem_read()
496 u16 src_offset = ptd_offset + slot * sizeof(*ptd); in isp1760_ptd_read() local
499 isp1760_reg_write(priv->regs, ISP176x_HC_MEMORY, src_offset); in isp1760_ptd_read()
502 bank_reads8(priv->base, src_offset, ISP_BANK_0, (void *)ptd, in isp1760_ptd_read()
[all …]
/drivers/crypto/ccp/
A Dccp-dmaengine.c366 unsigned int src_offset, src_len; in ccp_create_desc() local
385 src_offset = 0; in ccp_create_desc()
401 src_offset = 0; in ccp_create_desc()
433 ccp_pt->src_dma = sg_dma_address(src_sg) + src_offset; in ccp_create_desc()
450 src_offset += len; in ccp_create_desc()
/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
A Dbcmsdh.c383 unsigned int max_req_sz, src_offset, dst_offset; in brcmf_sdiod_sglist_rw() local
488 src_offset = 0; in brcmf_sdiod_sglist_rw()
497 if (req_sz > src->len - src_offset) in brcmf_sdiod_sglist_rw()
498 req_sz = src->len - src_offset; in brcmf_sdiod_sglist_rw()
500 orig_data = src->data + src_offset; in brcmf_sdiod_sglist_rw()
504 src_offset += req_sz; in brcmf_sdiod_sglist_rw()
505 if (src_offset == src->len) { in brcmf_sdiod_sglist_rw()
506 src_offset = 0; in brcmf_sdiod_sglist_rw()
/drivers/net/ethernet/mellanox/mlxsw/
A Dspectrum_acl_ctcam.c29 u16 src_offset, u16 dst_offset, u16 size) in mlxsw_sp_acl_ctcam_region_move() argument
34 region->tcam_region_info, src_offset, in mlxsw_sp_acl_ctcam_region_move()
/drivers/net/ethernet/intel/i40e/
A Di40e_ethtool.c3937 u16 src_offset) in i40e_find_flex_offset() argument
3947 if (entry->src_offset == src_offset) in i40e_find_flex_offset()
3976 u16 src_offset, in i40e_add_flex_offset() argument
3985 new_pit->src_offset = src_offset; in i40e_add_flex_offset()
3992 if (new_pit->src_offset < entry->src_offset) { in i40e_add_flex_offset()
4001 if (new_pit->src_offset == entry->src_offset) { in i40e_add_flex_offset()
4311 u16 index, src_offset = 0; in i40e_check_fdir_input_set() local
4582 src_offset); in i40e_check_fdir_input_set()
4596 src_offset); in i40e_check_fdir_input_set()
4646 pit_index, src_offset); in i40e_check_fdir_input_set()
[all …]

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