| /drivers/misc/ |
| A D | atmel-ssc.c | 29 struct ssc_device *ssc; in ssc_request() local
52 if (ssc->user) { in ssc_request()
57 ssc->user++; in ssc_request()
62 return ssc; in ssc_request()
71 if (ssc->user) in ssc_free()
72 ssc->user--; in ssc_free()
197 if (!ssc) { in ssc_probe()
202 ssc->pdev = pdev; in ssc_probe()
234 if (ssc->irq < 0) { in ssc_probe()
236 return ssc->irq; in ssc_probe()
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| A D | Makefile | 11 obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o
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| /drivers/hid/ |
| A D | hid-saitek.c | 40 struct saitek_sc *ssc; in saitek_probe() local
43 ssc = devm_kzalloc(&hdev->dev, sizeof(*ssc), GFP_KERNEL); in saitek_probe()
44 if (ssc == NULL) { in saitek_probe()
49 ssc->quirks = quirks; in saitek_probe()
50 ssc->mode = -1; in saitek_probe()
52 hid_set_drvdata(hdev, ssc); in saitek_probe()
111 if (mode != ssc->mode) { in saitek_raw_event()
113 if (ssc->mode != -1) { in saitek_raw_event()
117 ssc->mode = mode; in saitek_raw_event()
136 if (ssc->mode != -1) { in saitek_raw_event()
[all …]
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| /drivers/clk/ |
| A D | clk-renesas-pcie.c | 206 unsigned int amp, ssc; in rs9_get_common_config() local
231 ret = of_property_read_u32(np, "renesas,out-spread-spectrum", &ssc); in rs9_get_common_config()
233 if (ssc == 100000) /* 100% ... no spread (default) */ in rs9_get_common_config()
235 else if (ssc == 99750) /* -0.25% ... down spread */ in rs9_get_common_config()
237 else if (ssc == 99500) /* -0.50% ... down spread */ in rs9_get_common_config()
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| A D | clk-stm32f4.c | 695 struct stm32f4_pll_ssc *ssc = &pll->ssc_conf; in stm32f4_pll_set_ssc() local
703 modeper = DIV_ROUND_CLOSEST(parent_rate, 4 * ssc->mod_freq); in stm32f4_pll_set_ssc()
704 incstep = DIV_ROUND_CLOSEST(((1 << 15) - 1) * ssc->mod_depth * ndiv, in stm32f4_pll_set_ssc()
710 if (ssc->mod_type) in stm32f4_pll_set_ssc()
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| /drivers/mmc/host/ |
| A D | sdhci-pci-gli.c | 537 u32 ssc; in gl9750_set_ssc() local
541 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC); in gl9750_set_ssc()
544 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM; in gl9750_set_ssc()
547 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm); in gl9750_set_ssc()
548 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC); in gl9750_set_ssc()
734 u32 ssc; in gl9755_set_ssc() local
738 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc); in gl9755_set_ssc()
741 ssc &= ~PCI_GLI_9755_PLLSSC_PPM; in gl9755_set_ssc()
744 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm); in gl9755_set_ssc()
1103 u32 ssc; in gl9767_set_ssc() local
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| /drivers/phy/xilinx/ |
| A D | phy-zynqmp.c | 426 const struct xpsgtr_ssc *ssc; in xpsgtr_configure_pll() local
429 ssc = xpsgtr_find_sscs(gtr_phy); in xpsgtr_configure_pll()
430 if (!ssc) in xpsgtr_configure_pll()
433 step_size = ssc->step_size; in xpsgtr_configure_pll()
436 PLL_FREQ_MASK, ssc->pll_ref_clk); in xpsgtr_configure_pll()
462 STEPS_0_MASK, ssc->steps & STEPS_0_MASK); in xpsgtr_configure_pll()
467 (ssc->steps >> STEP_SIZE_SHIFT) & STEPS_1_MASK); in xpsgtr_configure_pll()
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| /drivers/phy/cadence/ |
| A D | phy-cadence-torrent.c | 757 if (ssc) in cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz()
774 if (ssc) in cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz()
790 if (ssc) in cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz()
805 if (ssc) in cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz()
810 if (ssc) { in cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz()
875 if (ssc) in cdns_torrent_dp_pma_cmn_vco_cfg_25mhz()
890 if (ssc) in cdns_torrent_dp_pma_cmn_vco_cfg_25mhz()
904 if (ssc) in cdns_torrent_dp_pma_cmn_vco_cfg_25mhz()
917 if (ssc) in cdns_torrent_dp_pma_cmn_vco_cfg_25mhz()
925 if (ssc) { in cdns_torrent_dp_pma_cmn_vco_cfg_25mhz()
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| A D | phy-cadence-sierra.c | 549 enum cdns_sierra_ssc_mode ssc = ins->ssc_mode; in cdns_sierra_phy_init() local
564 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc]; in cdns_sierra_phy_init()
574 phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_type][TYPE_NONE][ssc]; in cdns_sierra_phy_init()
586 pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc]; in cdns_sierra_phy_init()
596 pma_ln_vals = init_data->pma_ln_vals[phy_type][TYPE_NONE][ssc]; in cdns_sierra_phy_init()
1258 enum cdns_sierra_ssc_mode ssc; in cdns_sierra_phy_configure_multilink() local
1305 ssc = sp->phys[node].ssc_mode; in cdns_sierra_phy_configure_multilink()
1309 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc]; in cdns_sierra_phy_configure_multilink()
1319 phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_t1][phy_t2][ssc]; in cdns_sierra_phy_configure_multilink()
1331 pma_cmn_vals = init_data->pma_cmn_vals[phy_t1][phy_t2][ssc]; in cdns_sierra_phy_configure_multilink()
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| /drivers/gpu/drm/bridge/cadence/ |
| A D | cdns-mhdp8546-core.h | 296 bool ssc; member
305 bool ssc; member
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| A D | cdns-mhdp8546-core.c | 593 return mhdp->host.ssc && mhdp->sink.ssc; in cdns_mhdp_get_ssc_supported()
835 phy_cfg.dp.ssc = cdns_mhdp_get_ssc_supported(mhdp); in cdns_mhdp_link_training_init()
1003 phy_cfg.dp.ssc = cdns_mhdp_get_ssc_supported(mhdp); in cdns_mhdp_link_training_channel_eq()
1124 phy_cfg.dp.ssc = cdns_mhdp_get_ssc_supported(mhdp); in cdns_mhdp_link_training_cr()
1327 mhdp->host.ssc = false; in cdns_mhdp_fill_host_caps()
1339 mhdp->sink.ssc = !!(dpcd[DP_MAX_DOWNSPREAD] & in cdns_mhdp_fill_sink_caps()
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| /drivers/bus/ |
| A D | Makefile | 29 obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o
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| /drivers/pci/controller/ |
| A D | pcie-brcmstb.c | 292 bool ssc; member
382 int pll, ssc; in brcm_pcie_set_ssc() local
409 ssc = FIELD_GET(SSC_STATUS_SSC_MASK, tmp); in brcm_pcie_set_ssc()
412 return ssc && pll ? 0 : -EIO; in brcm_pcie_set_ssc()
1377 if (pcie->ssc) { in brcm_pcie_start_link()
1902 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); in brcm_pcie_probe()
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| /drivers/phy/st/ |
| A D | phy-miphy28lp.c | 211 bool ssc; member
667 if (miphy_phy->ssc) in miphy28lp_configure_sata()
703 if (miphy_phy->ssc) in miphy28lp_configure_pcie()
1147 miphy_phy->ssc = of_property_read_bool(np, "st,ssc-on"); in miphy28lp_of_probe()
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| /drivers/phy/mediatek/ |
| A D | phy-mtk-dp.c | 138 TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN : 0); in mtk_dp_phy_configure()
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| /drivers/gpu/drm/i915/display/ |
| A D | intel_display_core.h | 134 int ssc; member
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| A D | intel_dp_mst.c | 178 bool ssc, int dsc_slice_count, int bpp_x16) in intel_dp_mst_bw_overhead() argument
186 flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0; in intel_dp_mst_bw_overhead()
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| A D | intel_dpll_mgr.c | 1021 refclk = display->dpll.ref_clks.ssc; in hsw_ddi_wrpll_get_freq()
1246 display->dpll.ref_clks.ssc = 135000; in hsw_update_dpll_ref_clks()
2452 display->dpll.ref_clks.ssc = 100000; in bxt_update_dpll_ref_clks()
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| A D | intel_display_debugfs.c | 630 display->dpll.ref_clks.ssc); in i915_shared_dplls_info()
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| /drivers/spi/ |
| A D | Makefile | 77 obj-$(CONFIG_SPI_LANTIQ_SSC) += spi-lantiq-ssc.o
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| /drivers/phy/qualcomm/ |
| A D | phy-qcom-edp.c | 761 if (edp->dp_opts.ssc) { in qcom_edp_phy_power_on()
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| /drivers/phy/rockchip/ |
| A D | phy-rockchip-usbdp.c | 1250 FIELD_PREP(CMN_ROPLL_SSC_EN, dp->ssc)); in rk_udphy_dp_phy_configure()
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| A D | phy-rockchip-samsung-hdptx.c | 1589 if (dp->ssc) { in rk_hdptx_phy_set_rate()
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| /drivers/gpu/drm/mediatek/ |
| A D | mtk_dp.c | 1266 .ssc = mtk_dp->train_info.sink_ssc, in mtk_dp_phy_configure()
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| /drivers/gpu/drm/msm/dp/ |
| A D | dp_ctrl.c | 1787 ctrl->phy_opts.dp.ssc = drm_dp_max_downspread(dpcd); in msm_dp_ctrl_enable_mainlink_clocks()
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