Searched refs:start_mmioaddr (Results 1 – 4 of 4) sorted by relevance
| /drivers/gpu/drm/i915/display/ |
| A D | intel_flipq.c | 104 flipq->start_mmioaddr = intel_pipedmc_start_mmioaddr(crtc) + intel_flipq_offset(flipq_id); in intel_flipq_crtc_init()
109 flipq_id, flipq->start_mmioaddr); in intel_flipq_crtc_init()
218 flipq->start_mmioaddr); in intel_flipq_dump()
221 intel_de_read(display, PIPEDMC_FQ_RAM(flipq->start_mmioaddr, i))); in intel_flipq_dump()
293 u32 start_mmioaddr = intel_pipedmc_start_mmioaddr(crtc); in intel_flipq_enable() local
296 intel_de_write(display, PTL_PIPEDMC_EXEC_TIME_LINES(start_mmioaddr), in intel_flipq_enable()
298 intel_de_write(display, PTL_PIPEDMC_END_OF_EXEC_GB(start_mmioaddr), in intel_flipq_enable()
347 intel_de_write(display, PIPEDMC_FQ_RAM(flipq->start_mmioaddr, flipq->tail * in intel_flipq_write()
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| A D | intel_dmc_regs.h | 551 #define PIPEDMC_FQ_RAM(start_mmioaddr, i) _MMIO((start_mmioaddr) + (i) * 4) argument
584 #define PTL_PIPEDMC_EXEC_TIME_LINES(start_mmioaddr) _MMIO((start_mmioaddr) + 0x6b8) argument
585 #define PTL_PIPEDMC_END_OF_EXEC_GB(start_mmioaddr) _MMIO((start_mmioaddr) + 0x6c0) argument
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| A D | intel_dmc.c | 79 u32 start_mmioaddr; member
369 u32 start_mmioaddr; member
607 DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i), in dmc_load_program()
626 found = intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, 0)); in assert_dmc_loaded()
996 u32 mmio_count, mmio_count_max, start_mmioaddr; in parse_dmc_fw_header() local
1023 start_mmioaddr = v3->start_mmioaddr; in parse_dmc_fw_header()
1037 start_mmioaddr = DMC_V1_MMIO_START_RANGE; in parse_dmc_fw_header()
1076 dmc_info->start_mmioaddr = start_mmioaddr; in parse_dmc_fw_header()
1590 intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); in intel_dmc_debugfs_status_show()
1679 return dmc ? dmc->dmc_info[dmc_id].start_mmioaddr : 0; in intel_pipedmc_start_mmioaddr()
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| A D | intel_display_types.h | 1385 u32 start_mmioaddr; member
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