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Searched refs:stream_status (Results 1 – 25 of 36) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/core/
A Ddc_state.c438 state->stream_status[i] = state->stream_status[i + 1]; in dc_state_remove_stream()
521 stream_status->plane_states[stream_status->plane_count] = in dc_state_add_plane()
546 stream_status = &state->stream_status[i]; in dc_state_remove_plane()
574 stream_status->plane_states[i] = stream_status->plane_states[i + 1]; in dc_state_remove_plane()
576 stream_status->plane_states[stream_status->plane_count] = NULL; in dc_state_remove_plane()
603 stream_status = &state->stream_status[i]; in dc_state_rem_all_planes_for_stream()
882 stream_status = &state->stream_status[i]; in dc_state_rem_all_phantom_planes_for_stream()
996 if (stream_status) { in dc_state_set_stream_subvp_cursor_limit()
1010 if (stream_status) { in dc_state_get_stream_subvp_cursor_limit()
1025 if (stream_status) { in dc_state_set_stream_cursor_subvp_limit()
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A Ddc.c1256 if (!stream_status) in dc_get_visual_confirm_for_stream()
2908 if (stream_status == NULL || stream_status->plane_count != surface_count) in check_update_surfaces_for_stream()
3041 return &ctx->stream_status[i]; in stream_get_status()
3433 if (!stream_status) { in update_planes_and_stream_state()
3996 } else if (stream_status) { in commit_planes_for_stream_fast()
4010 stream_status, in commit_planes_for_stream_fast()
4261 stream_status = in commit_planes_for_stream()
4618 struct dc_stream_status *stream_status; in force_vsync_flip_in_minimal_transition_context() local
4621 stream_status = &context->stream_status[i]; in force_vsync_flip_in_minimal_transition_context()
5012 struct dc_stream_status *stream_status; in full_update_required() local
[all …]
A Ddc_hw_sequencer.c729 struct dc_stream_status *stream_status, in hwss_build_fast_sequence() argument
754 plane->flip_immediate && stream_status->mall_stream_config.type == SUBVP_MAIN; in hwss_build_fast_sequence()
801 stream_status->mall_stream_config.type == SUBVP_MAIN) { in hwss_build_fast_sequence()
893 plane->flip_immediate && stream_status->mall_stream_config.type == SUBVP_MAIN; in hwss_build_fast_sequence()
A Ddc_stream.c516 struct dc_stream_status *stream_status = dc_stream_get_status(stream); in dc_stream_add_writeback() local
518 if (stream_status) in dc_stream_add_writeback()
519 dwb->otg_inst = stream_status->primary_otg_inst; in dc_stream_add_writeback()
A Ddc_resource.c2428 if (state->stream_status[stream_idx].mall_stream_config.type != SUBVP_MAIN) in resource_log_pipe_topology_update()
2432 state->stream_status[stream_idx].mall_stream_config.paired_stream); in resource_log_pipe_topology_update()
3969 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst; in resource_map_pool_resources()
3970 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst; in resource_map_pool_resources()
3971 context->stream_status[i].audio_inst = in resource_map_pool_resources()
3995 struct dc_stream_status *stream_status = NULL; in planes_changed_for_existing_stream() local
3999 stream_status = &context->stream_status[i]; in planes_changed_for_existing_stream()
4004 if (!stream_status) { in planes_changed_for_existing_stream()
4016 if (set[i].plane_count != stream_status->plane_count) in planes_changed_for_existing_stream()
4020 if (set[i].plane_states[j] != stream_status->plane_states[j]) in planes_changed_for_existing_stream()
/drivers/gpu/drm/amd/display/dc/clk_mgr/
A Dclk_mgr.c62 const struct dc_stream_status *stream_status = &context->stream_status[i]; in clk_mgr_helper_get_active_display_cnt() local
70 …if (!stream->dpms_off || dc->is_switch_in_progress_dest || (stream_status && stream_status->plane_… in clk_mgr_helper_get_active_display_cnt()
85 const struct dc_stream_status stream_status = context->stream_status[i]; in clk_mgr_helper_get_active_plane_cnt() local
90 total_plane_count += stream_status.plane_count; in clk_mgr_helper_get_active_plane_cnt()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_utils.c44 for (j = 0; j < state->stream_status[i].plane_count; j++) { in dml21_get_plane_id()
45 if (state->stream_status[i].plane_states[j] == plane) { in dml21_get_plane_id()
402 if (context->stream_status[i].plane_count == 0 || in dml21_build_fams2_programming()
435 static_base_state->stream_v1.base.num_planes = context->stream_status[i].plane_count; in dml21_build_fams2_programming()
436 static_base_state->stream_v1.base.otg_inst = context->stream_status[i].primary_otg_inst; in dml21_build_fams2_programming()
439 for (j = 0; j < context->stream_status[i].plane_count; j++) { in dml21_build_fams2_programming()
443 context->res_ctx.pipe_ctx[k].plane_state == context->stream_status[i].plane_states[j]) { in dml21_build_fams2_programming()
A Ddml21_translation_helper.c603 struct dc_stream_status *stream_status) in populate_dml21_stream_overrides_from_stream_state() argument
630 stream_status->mall_stream_config.cursor_size_limit_subvp; in populate_dml21_stream_overrides_from_stream_state()
999 for (j = 0; j < context->stream_status[i].plane_count; j++) { in dml21_wrapper_get_plane_id()
1000 if (context->stream_status[i].plane_states[j] == plane) { in dml21_wrapper_get_plane_id()
1103 …[disp_cfg_stream_location], context->streams[stream_index], &context->stream_status[stream_index]); in dml21_map_dc_state_into_dml_display_cfg()
1112 if (context->stream_status[stream_index].plane_count == 0) { in dml21_map_dc_state_into_dml_display_cfg()
1118 …for (plane_index = 0; plane_index < context->stream_status[stream_index].plane_count; plane_index+… in dml21_map_dc_state_into_dml_display_cfg()
1119 …play_cfg(dml_ctx, context->streams[stream_index]->stream_id, context->stream_status[stream_index].… in dml21_map_dc_state_into_dml_display_cfg()
1126 …dispcfg->plane_descriptors[disp_cfg_plane_location].surface, context->stream_status[stream_index].… in dml21_map_dc_state_into_dml_display_cfg()
1127 …x, &dml_dispcfg->plane_descriptors[disp_cfg_plane_location], context->stream_status[stream_index].… in dml21_map_dc_state_into_dml_display_cfg()
[all …]
A Ddml21_wrapper.c182 for (plane_idx = 0; plane_idx < context->stream_status[stream_idx].plane_count; plane_idx++) { in dml21_prepare_mcache_params()
183 …isplay_cfg(dml_ctx, context->streams[stream_idx]->stream_id, context->stream_status[stream_idx].pl… in dml21_prepare_mcache_params()
/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_dc_resource_mgmt.c69 for (j = 0; j < state->stream_status[i].plane_count; j++) { in get_plane_id()
70 if (state->stream_status[i].plane_states[j] == plane && in get_plane_id()
931 const struct dc_stream_status *status = &state->stream_status[stream_idx]; in populate_mpc_factors_for_stream()
1029 …&state->stream_status[i], ctx->pipe_combine_scratch.odm_factors[i], ctx->pipe_combine_scratch.mpc_… in map_dc_pipes_with_callbacks()
1032 …&state->stream_status[i], ctx->pipe_combine_scratch.odm_factors[i], ctx->pipe_combine_scratch.mpc_… in map_dc_pipes_with_callbacks()
1115 if (state->stream_status[stream_index].plane_count == 0) { in dml2_map_dc_pipes()
1119 …for (plane_index = 0; plane_index < state->stream_status[stream_index].plane_count; plane_index++)… in dml2_map_dc_pipes()
1121 if (get_plane_id(ctx, state, state->stream_status[stream_index].plane_states[plane_index], in dml2_map_dc_pipes()
1147 …state->stream_status[stream_index].plane_states[plane_index], plane_index, &scratch, existing_stat… in dml2_map_dc_pipes()
A Ddml2_mall_phantom.c167 if (context->stream_status[i].plane_count > 1) in mpo_in_use()
815 struct dc_stream_status *stream_status = NULL; in remove_all_phantom_planes_for_stream() local
820 stream_status = &context->stream_status[i]; in remove_all_phantom_planes_for_stream()
824 if (stream_status == NULL) { in remove_all_phantom_planes_for_stream()
828 old_plane_count = stream_status->plane_count; in remove_all_phantom_planes_for_stream()
831 del_planes[i] = stream_status->plane_states[i]; in remove_all_phantom_planes_for_stream()
A Ddml2_translation_helper.c1157 for (j = 0; j < context->stream_status[i].plane_count; j++) { in get_plane_id()
1158 if (context->stream_status[i].plane_states[j] == plane && in get_plane_id()
1353 if (context->stream_status[i].plane_count == 0) { in map_dc_state_into_dml_display_cfg()
1364 for (j = 0; j < context->stream_status[i].plane_count; j++) { in map_dc_state_into_dml_display_cfg()
1366 …context->stream_status[i].plane_states[j], context, dml_dispcfg, context->streams[i]->stream_id, j… in map_dc_state_into_dml_display_cfg()
1373 …ctx.project, &dml_dispcfg->surface, disp_cfg_plane_location, context->stream_status[i].plane_state… in map_dc_state_into_dml_display_cfg()
1376 context->stream_status[i].plane_states[j], context, in map_dc_state_into_dml_display_cfg()
1393 …if (get_plane_id(dml2, context, context->stream_status[i].plane_states[j], context->streams[i]->st… in map_dc_state_into_dml_display_cfg()
/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
A Ddcn32_hwseq.c203 if ((dc->current_state->stream_status[i].plane_count) && in dcn32_check_no_memory_request_for_cab()
269 dc->current_state->stream_status[i].plane_count > 0))) in dcn32_apply_idle_power_optimizations()
299 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) { in dcn32_apply_idle_power_optimizations()
300 plane = dc->current_state->stream_status[i].plane_states[j]; in dcn32_apply_idle_power_optimizations()
609 struct dc_stream_status *stream_status = NULL; in dcn32_update_force_pstate() local
612 stream_status = dc_state_get_stream_status(context, pipe->stream); in dcn32_update_force_pstate()
615 (stream_status && stream_status->fpo_in_use))) { in dcn32_update_force_pstate()
629 struct dc_stream_status *stream_status = NULL; in dcn32_update_force_pstate() local
645 stream_status = dc_state_get_stream_status(context, pipe->stream); in dcn32_update_force_pstate()
650 (stream_status && stream_status->fpo_in_use)) && in dcn32_update_force_pstate()
/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
A Ddcn30_hwseq.c578 struct dc_stream_status *stream_status = NULL; in dcn30_program_all_writeback_pipes_in_tree() local
585 stream_status = &context->stream_status[i_stream]; in dcn30_program_all_writeback_pipes_in_tree()
589 ASSERT(stream_status); in dcn30_program_all_writeback_pipes_in_tree()
926 if (dc->current_state->stream_status[i].plane_count) in dcn30_apply_idle_power_optimizations()
944 plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL); in dcn30_apply_idle_power_optimizations()
966 dc->current_state->stream_status[0].plane_count == 1 && in dcn30_apply_idle_power_optimizations()
/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource_helpers.c189 if (context->stream_status[i].plane_count > 1) in dcn32_mpo_in_use()
252 if (context->stream_status[i].plane_count > 1) in override_det_for_subvp()
334 if (context->stream_status[i].plane_count > 0) in dcn32_determine_det_override()
335 plane_segments = stream_segments / context->stream_status[i].plane_count; in dcn32_determine_det_override()
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddcn30_fpu.c314 struct dc_stream_status *stream_status = NULL; in dcn30_fpu_calculate_wm_and_dlg() local
320 stream_status = NULL; in dcn30_fpu_calculate_wm_and_dlg()
322 stream_status = dc_state_get_stream_status(context, context->streams[i]); in dcn30_fpu_calculate_wm_and_dlg()
323 if (stream_status) in dcn30_fpu_calculate_wm_and_dlg()
324 stream_status->fpo_in_use = false; in dcn30_fpu_calculate_wm_and_dlg()
/drivers/gpu/drm/amd/display/dc/
A Ddc_dmub_srv.c446 struct dc_stream_status *stream_status = NULL; in dc_dmub_srv_p_state_delegate() local
470 stream_status = dc_state_get_stream_status(context, pipe->stream); in dc_dmub_srv_p_state_delegate()
471 if (stream_status && !stream_status->fpo_in_use) { in dc_dmub_srv_p_state_delegate()
485 stream_status = dc_state_get_stream_status(context, pipe->stream); in dc_dmub_srv_p_state_delegate()
486 if (stream_status && stream_status->fpo_in_use) { in dc_dmub_srv_p_state_delegate()
1851 struct dc_stream_status *stream_status = dc_stream_get_status(stream); in dc_dmub_srv_fams2_passthrough_flip() local
1853 if (surface_count <= 0 || stream_status == NULL) in dc_dmub_srv_fams2_passthrough_flip()
1878 if (stream_status) in dc_dmub_srv_fams2_passthrough_flip()
1879 cmds[num_cmds].fams2_flip.flip_info.otg_inst = stream_status->primary_otg_inst; in dc_dmub_srv_fams2_passthrough_flip()
A Ddc_stream.h478 const struct dc_stream_status *stream_status);
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c1379 if (context->stream_status[0].plane_count != 1) in should_apply_odm_power_optimization()
2322 struct dc_stream_status *stream_status = NULL; in dcn32_calculate_wm_and_dlg_fpu() local
2357 stream_status = NULL; in dcn32_calculate_wm_and_dlg_fpu()
2360 if (stream_status) in dcn32_calculate_wm_and_dlg_fpu()
2361 stream_status->fpo_in_use = false; in dcn32_calculate_wm_and_dlg_fpu()
2370 if (stream_status) in dcn32_calculate_wm_and_dlg_fpu()
2371 stream_status->fpo_in_use = true; in dcn32_calculate_wm_and_dlg_fpu()
2409 stream_status = NULL; in dcn32_calculate_wm_and_dlg_fpu()
2412 if (stream_status) in dcn32_calculate_wm_and_dlg_fpu()
2413 stream_status->fpo_in_use = false; in dcn32_calculate_wm_and_dlg_fpu()
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn10/
A Ddcn10_resource.c1163 if (context->stream_status[i].plane_count == 0) in dcn10_validate_global()
1166 if (context->stream_status[i].plane_count > 2) in dcn10_validate_global()
1169 if (context->stream_status[i].plane_count > 1) in dcn10_validate_global()
1172 for (j = 0; j < context->stream_status[i].plane_count; j++) { in dcn10_validate_global()
1174 context->stream_status[i].plane_states[j]; in dcn10_validate_global()
/drivers/gpu/drm/amd/display/dc/resource/dce100/
A Ddce100_resource.c870 if (context->stream_status[i].plane_count == 0) in dce100_validate_surface_sets()
873 if (context->stream_status[i].plane_count > 1) in dce100_validate_surface_sets()
876 if (context->stream_status[i].plane_states[0]->format in dce100_validate_surface_sets()
/drivers/gpu/drm/amd/display/dc/resource/dce110/
A Ddce110_resource.c1053 if (context->stream_status[i].plane_count == 0) in dce110_validate_surface_sets()
1056 if (context->stream_status[i].plane_count > 2) in dce110_validate_surface_sets()
1059 for (j = 0; j < context->stream_status[i].plane_count; j++) { in dce110_validate_surface_sets()
1061 context->stream_status[i].plane_states[j]; in dce110_validate_surface_sets()
/drivers/gpu/drm/amd/display/dc/resource/dce112/
A Ddce112_resource.c999 if (context->stream_status[i].plane_count == 0) in dce112_validate_surface_sets()
1002 if (context->stream_status[i].plane_count > 1) in dce112_validate_surface_sets()
1005 if (context->stream_status[i].plane_states[0]->format in dce112_validate_surface_sets()
/drivers/gpu/drm/amd/display/dc/resource/dce60/
A Ddce60_resource.c897 if (context->stream_status[i].plane_count == 0) in dce60_validate_surface_sets()
900 if (context->stream_status[i].plane_count > 1) in dce60_validate_surface_sets()
903 if (context->stream_status[i].plane_states[0]->format in dce60_validate_surface_sets()
/drivers/gpu/drm/amd/display/dc/resource/dce80/
A Ddce80_resource.c903 if (context->stream_status[i].plane_count == 0) in dce80_validate_surface_sets()
906 if (context->stream_status[i].plane_count > 1) in dce80_validate_surface_sets()
909 if (context->stream_status[i].plane_states[0]->format in dce80_validate_surface_sets()

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