Home
last modified time | relevance | path

Searched refs:surface (Results 1 – 25 of 36) sorted by relevance

12

/drivers/gpu/drm/amd/display/dc/core/
A Ddc.c3058 surface->time.time_elapsed_in_us[surface->time.index] = in copy_surface_update_to_plane()
3073 surface->dst_rect = in copy_surface_update_to_plane()
3075 surface->src_rect = in copy_surface_update_to_plane()
3084 surface->format = in copy_surface_update_to_plane()
3096 surface->visible = in copy_surface_update_to_plane()
3104 surface->dcc = in copy_surface_update_to_plane()
3145 surface->mcm_luts.shaper = &surface->in_shaper_func; in copy_surface_update_to_plane()
3165 surface->mcm_luts.lut1d_func = &surface->blend_tf; in copy_surface_update_to_plane()
3169 surface->lut_bank_a = !surface->lut_bank_a; in copy_surface_update_to_plane()
3516 struct dc_plane_state *surface = srf_updates[i].surface; in update_planes_and_stream_state() local
[all …]
/drivers/gpu/drm/vmwgfx/
A Dvmwgfx_cursor_plane.c81 if (WARN_ON(!surface || !surface->snooper.image)) in vmw_cursor_plane_update_legacy()
84 if (vps->cursor.legacy.id != surface->snooper.id) { in vmw_cursor_plane_update_legacy()
88 vps->cursor.legacy.id = surface->snooper.id; in vmw_cursor_plane_update_legacy()
97 if (surface && surface->snooper.image) in vmw_cursor_update_type()
601 struct vmw_surface *surface; in vmw_cursor_plane_prepare_fb() local
612 vps->uo.surface = NULL; in vmw_cursor_plane_prepare_fb()
622 surface = vmw_user_object_surface(&vps->uo); in vmw_cursor_plane_prepare_fb()
623 if (!surface || vps->cursor.legacy.id == surface->snooper.id) in vmw_cursor_plane_prepare_fb()
696 struct vmw_surface *surface = NULL; in vmw_cursor_plane_atomic_check() local
725 surface = vmw_user_object_surface(&vps->uo); in vmw_cursor_plane_atomic_check()
[all …]
A Dvmwgfx_kms.c510 struct vmw_surface *surface; in vmw_kms_new_framebuffer_surface() local
726 struct vmw_surface *surface; in vmw_kms_fb_create() local
768 if (!ret && surface && surface->res.func->dirty_alloc) { in vmw_kms_fb_create()
769 surface->res.coherent = true; in vmw_kms_fb_create()
770 ret = surface->res.func->dirty_alloc(&surface->res); in vmw_kms_fb_create()
1070 struct vmw_surface *surface, in vmw_kms_generic_present() argument
1085 struct vmw_surface *surface, in vmw_kms_present() argument
1940 else if (uo->surface) in vmw_user_object_ref()
1949 else if (uo->surface) in vmw_user_object_unref()
1958 else if (uo->surface) in vmw_user_object_buffer()
[all …]
A Dvmwgfx_vkms.c130 surf = vmw_surface_reference(du->vkms.surface); in crc_generate_worker()
181 has_surface = du->vkms.surface != NULL; in vmw_vkms_vblank_simulate()
311 du->vkms.surface = NULL; in vmw_vkms_disable_vblank()
330 du->vkms.surface = NULL; in vmw_vkms_crtc_init()
338 if (du->vkms.surface) in vmw_vkms_crtc_cleanup()
339 vmw_surface_unreference(&du->vkms.surface); in vmw_vkms_crtc_cleanup()
501 if (vmw->vkms_enabled && du->vkms.surface != surf) { in vmw_vkms_set_crc_surface()
503 if (du->vkms.surface) in vmw_vkms_set_crc_surface()
504 vmw_surface_unreference(&du->vkms.surface); in vmw_vkms_set_crc_surface()
506 du->vkms.surface = vmw_surface_reference(surf); in vmw_vkms_set_crc_surface()
A Dvmwgfx_ioctl.c178 struct vmw_surface *surface; in vmw_present_ioctl() local
229 surface = vmw_res_to_srf(res); in vmw_present_ioctl()
231 vfb, surface, arg->sid, in vmw_present_ioctl()
236 vmw_surface_unreference(&surface); in vmw_present_ioctl()
A Dvmwgfx_resource.c301 WARN_ON(uo->surface || uo->buffer); in vmw_user_object_lookup()
307 uo->surface = vmw_res_to_srf(res); in vmw_user_object_lookup()
311 uo->surface = NULL; in vmw_user_object_lookup()
314 uo->surface = vmw_lookup_surface_for_buffer(dev_priv, in vmw_user_object_lookup()
317 if (uo->surface) in vmw_user_object_lookup()
A Dvmwgfx_kms.h332 struct vmw_surface *surface; member
A Dvmwgfx_drv.h745 struct vmw_surface *surface; member
1036 struct vmw_surface *surface,
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_translation_helper.c718 surface->plane0.width = stream->timing.h_addressable; in populate_dml21_dummy_surface_cfg()
722 surface->plane0.pitch = ((surface->plane0.width + 127) / 128) * 128; in populate_dml21_dummy_surface_cfg()
723 surface->plane1.pitch = 0; in populate_dml21_dummy_surface_cfg()
724 surface->dcc.enable = false; in populate_dml21_dummy_surface_cfg()
725 surface->dcc.informative.dcc_rate_plane0 = 1.0; in populate_dml21_dummy_surface_cfg()
726 surface->dcc.informative.dcc_rate_plane1 = 1.0; in populate_dml21_dummy_surface_cfg()
729 surface->tiling = dml2_sw_64kb_2d; in populate_dml21_dummy_surface_cfg()
781 struct dml2_surface_cfg *surface, in populate_dml21_surface_config_from_plane_state() argument
790 surface->dcc.enable = plane_state->dcc.enable; in populate_dml21_surface_config_from_plane_state()
791 surface->dcc.informative.dcc_rate_plane0 = 1.0; in populate_dml21_surface_config_from_plane_state()
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/
A Ddisplay_mode_util.c594 dml_print("DML: surface_cfg: plane=%d, PitchY = %d\n", i, surface->PitchY[i]); in dml_print_dml_display_cfg_surface()
595 dml_print("DML: surface_cfg: plane=%d, SurfaceWidthY = %d\n", i, surface->SurfaceWidthY[i]); in dml_print_dml_display_cfg_surface()
596 dml_print("DML: surface_cfg: plane=%d, SurfaceHeightY = %d\n", i, surface->SurfaceHeightY[i]); in dml_print_dml_display_cfg_surface()
597 dml_print("DML: surface_cfg: plane=%d, PitchC = %d\n", i, surface->PitchC[i]); in dml_print_dml_display_cfg_surface()
598 dml_print("DML: surface_cfg: plane=%d, SurfaceWidthC = %d\n", i, surface->SurfaceWidthC[i]); in dml_print_dml_display_cfg_surface()
599 dml_print("DML: surface_cfg: plane=%d, SurfaceHeightC = %d\n", i, surface->SurfaceHeightC[i]); in dml_print_dml_display_cfg_surface()
600 dml_print("DML: surface_cfg: plane=%d, DCCEnable = %d\n", i, surface->DCCEnable[i]); in dml_print_dml_display_cfg_surface()
601 dml_print("DML: surface_cfg: plane=%d, DCCMetaPitchY = %d\n", i, surface->DCCMetaPitchY[i]); in dml_print_dml_display_cfg_surface()
602 dml_print("DML: surface_cfg: plane=%d, DCCMetaPitchC = %d\n", i, surface->DCCMetaPitchC[i]); in dml_print_dml_display_cfg_surface()
603 dml_print("DML: surface_cfg: plane=%d, DCCRateLuma = %f\n", i, surface->DCCRateLuma[i]); in dml_print_dml_display_cfg_surface()
[all …]
A Ddisplay_mode_core.c7595 mode_lib->ms.cache_display_cfg.surface.DCCEnable, in dml_core_mode_support()
8075 …dml_max(mode_lib->ms.cache_display_cfg.surface.PitchY[k], mode_lib->ms.cache_display_cfg.surface.S… in dml_core_mode_support()
8459 mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY, in dml_core_mode_programming()
8460 mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC, in dml_core_mode_programming()
8629 mode_lib->ms.cache_display_cfg.surface.DCCEnable, in dml_core_mode_programming()
8641 mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY, in dml_core_mode_programming()
8642 mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC, in dml_core_mode_programming()
9545 mode_lib->ms.cache_display_cfg.surface.DCCEnable, in dml_core_mode_programming()
9596 mode_lib->ms.cache_display_cfg.surface.DCCEnable, in dml_core_mode_programming()
9869 mode_lib->ms.cache_display_cfg.surface.DCCRateLuma, in dml_core_mode_programming()
[all …]
A Ddisplay_mode_util.h63 __DML_DLL_EXPORT__ void dml_print_dml_display_cfg_surface(const struct dml_surface_cfg_st *surface,…
A Ddml_display_rq_dlg_calc.c44 …enum dml_source_format_class source_format = mode_lib->ms.cache_display_cfg.surface.SourcePixelFor… in dml_rq_dlg_get_rq_reg()
45 …enum dml_swizzle_mode sw_mode = mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[plane_idx… in dml_rq_dlg_get_rq_reg()
203 …enum dml_source_format_class source_format = mode_lib->ms.cache_display_cfg.surface.SourcePixelFor… in dml_rq_dlg_get_dlg_reg()
/drivers/gpu/drm/radeon/
A Dradeon_asic.c235 .surface = {
303 .surface = {
399 .surface = {
467 .surface = {
535 .surface = {
603 .surface = {
671 .surface = {
739 .surface = {
807 .surface = {
875 .surface = {
[all …]
/drivers/platform/
A DMakefile14 obj-$(CONFIG_SURFACE_PLATFORMS) += surface/
A DKconfig16 source "drivers/platform/surface/Kconfig"
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/
A Ddml2_top_soc15.c532 if (!params->display_cfg->plane_descriptors[plane_index].surface.dcc.enable) in dml2_top_mcache_validate_admissability()
546 max_per_pipe_vp_p0 = plane->surface.plane0.width; in dml2_top_mcache_validate_admissability()
552 max_per_pipe_vp_p1 = plane->surface.plane1.width; in dml2_top_mcache_validate_admissability()
558 max_per_pipe_vp_p0 = plane->surface.plane0.width / mpc_combine_factor; in dml2_top_mcache_validate_admissability()
559 max_per_pipe_vp_p1 = plane->surface.plane1.width / mpc_combine_factor; in dml2_top_mcache_validate_admissability()
592 calculate_h_split_for_scaling_transform(plane->surface.plane0.width, in dml2_top_mcache_validate_admissability()
603 calculate_h_split_for_scaling_transform(plane->surface.plane1.width, in dml2_top_mcache_validate_admissability()
744 if (!params->display_config->plane_descriptors[i].surface.dcc.enable) { in dml2_top_mcache_calc_mcache_count_and_offsets()
1034 if (params->mcache_configurations[config_index].plane_descriptor->surface.dcc.enable) { in dml2_top_soc15_build_mcache_programming()
/drivers/gpu/drm/qxl/
A Dqxl_draw.c79 make_drawable(struct qxl_device *qdev, int surface, uint8_t type, in make_drawable() argument
92 drawable->surface_id = surface; /* Only primary for now */ in make_drawable()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
A Ddml2_core_dcn4_calcs.c4551 const struct dml2_surface_cfg *surface = &display_cfg->plane_descriptors[k].surface; in CalculateSurfaceSizeInMall() local
4743 if (display_cfg->plane_descriptors[k].surface.dcc.enable) in CalculateTarb()
8035 display_cfg->plane_descriptors[k].surface.tiling, in dml_core_mode_support()
8036 display_cfg->plane_descriptors[k].surface.plane0.pitch, in dml_core_mode_support()
8037 display_cfg->plane_descriptors[k].surface.plane1.pitch, in dml_core_mode_support()
10505 display_cfg->plane_descriptors[k].surface.tiling, in dml_core_mode_programming()
10506 display_cfg->plane_descriptors[k].surface.plane0.pitch, in dml_core_mode_programming()
10507 display_cfg->plane_descriptors[k].surface.plane1.pitch, in dml_core_mode_programming()
11615 display_cfg->plane_descriptors[k].surface.dcc.enable, in dml_core_mode_programming()
11625 display_cfg->plane_descriptors[k].surface.tiling, in dml_core_mode_programming()
[all …]
A Ddml2_core_dcn4.c652 …n_out->mcache_allocation->num_mcaches_plane0 - 1] = in_out->plane_descriptor->surface.plane0.width; in core_dcn4_calculate_mcache_allocation()
655 …n_out->mcache_allocation->num_mcaches_plane1 - 1] = in_out->plane_descriptor->surface.plane1.width; in core_dcn4_calculate_mcache_allocation()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
A Ddml_top_display_cfg_types.h351 struct dml2_surface_cfg surface; member
/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/
A Dcom.fuc416 // Calculates the hw swizzle mask and adjusts the surface's xcnt to match
515 // Setup to handle a tiled surface
536 // $p2: set if dst surface
666 // Setup to handle a linear surface
/drivers/platform/surface/
A DKconfig68 interface (/dev/surface/aggregator), which can be used by user-space
232 source "drivers/platform/surface/aggregator/Kconfig"
/drivers/hid/
A DMakefile175 obj-$(CONFIG_SURFACE_HID_CORE) += surface-hid/
/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm.c397 return sb->surface->layer_index - sa->surface->layer_index; in dm_plane_layer_index_cmp()
3329 bundle->surface_updates[m].surface = in dm_gpureset_commit_state()
3331 bundle->surface_updates[m].surface->force_full_update = in dm_gpureset_commit_state()
8970 struct dc_plane_state *surface, in update_freesync_state_on_stream() argument
8996 if (surface) { in update_freesync_state_on_stream()
8999 surface, in update_freesync_state_on_stream()
9393 bundle->surface_updates[planes_count].surface = dc_plane; in amdgpu_dm_commit_planes()
9486 bundle->surface_updates[planes_count].surface = dc_plane; in amdgpu_dm_commit_planes()
9488 if (!bundle->surface_updates[planes_count].surface) { in amdgpu_dm_commit_planes()
10335 dummy_updates[j].surface = status->plane_states[0]; in amdgpu_dm_atomic_commit_tail()

Completed in 143 milliseconds

12