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Searched refs:taps (Results 1 – 25 of 41) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/sspl/
A Ddc_spl_scl_easf_filters.c2257 if (taps == 6) in spl_dscl_get_easf_filter_coeffs_64p()
2332 if (taps == 6) in spl_dscl_get_easf_filter_coeffs_64p_s1_10()
2432 if (taps == 4) { in spl_get_reducer_gain6()
2451 if (taps == 4) { in spl_get_reducer_gain4()
2470 if (taps == 4) { in spl_get_gainRing6()
2489 if (taps == 4) { in spl_get_gainRing4()
2508 if (taps == 3) { in spl_get_3tap_dntilt_uptilt_offset()
2522 if (taps == 3) { in spl_get_3tap_uptilt_maxval()
2536 if (taps == 3) { in spl_get_3tap_dntilt_slope()
2550 if (taps == 3) { in spl_get_3tap_uptilt1_slope()
[all …]
A Ddc_spl_scl_easf_filters.h22 uint32_t spl_get_reducer_gain6(int taps, struct spl_fixed31_32 ratio);
23 uint32_t spl_get_reducer_gain4(int taps, struct spl_fixed31_32 ratio);
24 uint32_t spl_get_gainRing6(int taps, struct spl_fixed31_32 ratio);
25 uint32_t spl_get_gainRing4(int taps, struct spl_fixed31_32 ratio);
26 uint32_t spl_get_3tap_dntilt_uptilt_offset(int taps, struct spl_fixed31_32 ratio);
27 uint32_t spl_get_3tap_uptilt_maxval(int taps, struct spl_fixed31_32 ratio);
28 uint32_t spl_get_3tap_dntilt_slope(int taps, struct spl_fixed31_32 ratio);
29 uint32_t spl_get_3tap_uptilt1_slope(int taps, struct spl_fixed31_32 ratio);
30 uint32_t spl_get_3tap_uptilt2_slope(int taps, struct spl_fixed31_32 ratio);
31 uint32_t spl_get_3tap_uptilt2_offset(int taps, struct spl_fixed31_32 ratio);
[all …]
A Ddc_spl.c543 int taps, in spl_calculate_init_and_vp() argument
576 if (int_part < taps) { in spl_calculate_init_and_vp()
577 int_part = taps - int_part; in spl_calculate_init_and_vp()
849 struct spl_taps taps = spl_scratch->scl_data.taps; in spl_get_isharp_en() local
883 if ((taps.h_taps == 4 || taps.h_taps == 6) && in spl_get_isharp_en()
884 (taps.v_taps == 3 || taps.v_taps == 4 || taps.v_taps == 6)) in spl_get_isharp_en()
1217 dscl_prog_data->taps.v_taps = scl_data->taps.v_taps - 1; in spl_set_taps_data()
1218 dscl_prog_data->taps.h_taps = scl_data->taps.h_taps - 1; in spl_set_taps_data()
1219 dscl_prog_data->taps.v_taps_c = scl_data->taps.v_taps_c - 1; in spl_set_taps_data()
1220 dscl_prog_data->taps.h_taps_c = scl_data->taps.h_taps_c - 1; in spl_set_taps_data()
[all …]
A Ddc_spl_scl_filters.c1210 const uint16_t *spl_dscl_get_filter_coeffs_64p(int taps, struct spl_fixed31_32 ratio) in spl_dscl_get_filter_coeffs_64p() argument
1212 if (taps == 8) in spl_dscl_get_filter_coeffs_64p()
1214 else if (taps == 7) in spl_dscl_get_filter_coeffs_64p()
1216 else if (taps == 6) in spl_dscl_get_filter_coeffs_64p()
1218 else if (taps == 5) in spl_dscl_get_filter_coeffs_64p()
1220 else if (taps == 4) in spl_dscl_get_filter_coeffs_64p()
1222 else if (taps == 3) in spl_dscl_get_filter_coeffs_64p()
1224 else if (taps == 2) in spl_dscl_get_filter_coeffs_64p()
1226 else if (taps == 1) in spl_dscl_get_filter_coeffs_64p()
A Ddc_spl_isharp_filters.c514 const uint16_t *spl_dscl_get_blur_scale_coeffs_64p(int taps) in spl_dscl_get_blur_scale_coeffs_64p() argument
516 if (taps == 3) in spl_dscl_get_blur_scale_coeffs_64p()
518 else if (taps == 4) in spl_dscl_get_blur_scale_coeffs_64p()
520 else if (taps == 6) in spl_dscl_get_blur_scale_coeffs_64p()
529 const uint16_t *spl_dscl_get_blur_scale_coeffs_64p_s1_10(int taps) in spl_dscl_get_blur_scale_coeffs_64p_s1_10() argument
531 if (taps == 3) in spl_dscl_get_blur_scale_coeffs_64p_s1_10()
533 else if (taps == 4) in spl_dscl_get_blur_scale_coeffs_64p_s1_10()
535 else if (taps == 6) in spl_dscl_get_blur_scale_coeffs_64p_s1_10()
548 spl_dscl_get_blur_scale_coeffs_64p(data->taps.h_taps); in spl_set_blur_scale_data()
551 spl_dscl_get_blur_scale_coeffs_64p(data->taps.v_taps); in spl_set_blur_scale_data()
A Ddc_spl_isharp_filters.h39 const uint16_t *spl_dscl_get_blur_scale_coeffs_64p(int taps);
40 const uint16_t *spl_dscl_get_blur_scale_coeffs_64p_s1_10(int taps);
A Ddc_spl_scl_filters.h11 const uint16_t *spl_dscl_get_filter_coeffs_64p(int taps, struct spl_fixed31_32 ratio);
A Ddc_spl_types.h135 struct spl_taps taps; member
263 struct spl_taps taps; // TAPS - set based on scl_data.taps member
/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
A Ddcn10_dpp_dscl.c217 if (taps == 8) in dpp1_dscl_get_filter_coeffs_64p()
219 else if (taps == 7) in dpp1_dscl_get_filter_coeffs_64p()
221 else if (taps == 6) in dpp1_dscl_get_filter_coeffs_64p()
223 else if (taps == 5) in dpp1_dscl_get_filter_coeffs_64p()
225 else if (taps == 4) in dpp1_dscl_get_filter_coeffs_64p()
227 else if (taps == 3) in dpp1_dscl_get_filter_coeffs_64p()
229 else if (taps == 2) in dpp1_dscl_get_filter_coeffs_64p()
231 else if (taps == 1) in dpp1_dscl_get_filter_coeffs_64p()
242 uint32_t taps, in dpp1_dscl_set_scaler_filter() argument
297 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1); in dpp1_dscl_set_scl_filter()
[all …]
A Ddcn10_dpp.c155 scl_data->taps.h_taps = 4; in dpp1_get_optimal_number_of_taps()
157 scl_data->taps.h_taps = in_taps->h_taps; in dpp1_get_optimal_number_of_taps()
159 scl_data->taps.v_taps = 4; in dpp1_get_optimal_number_of_taps()
161 scl_data->taps.v_taps = in_taps->v_taps; in dpp1_get_optimal_number_of_taps()
163 scl_data->taps.v_taps_c = 2; in dpp1_get_optimal_number_of_taps()
165 scl_data->taps.v_taps_c = in_taps->v_taps_c; in dpp1_get_optimal_number_of_taps()
167 scl_data->taps.h_taps_c = 2; in dpp1_get_optimal_number_of_taps()
176 scl_data->taps.h_taps = 1; in dpp1_get_optimal_number_of_taps()
178 scl_data->taps.v_taps = 1; in dpp1_get_optimal_number_of_taps()
180 scl_data->taps.h_taps_c = 1; in dpp1_get_optimal_number_of_taps()
[all …]
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_transform.c122 if (data->taps.h_taps + data->taps.v_taps <= 2) { in setup_scaling_configuration()
156 if (data->taps.h_taps + data->taps.v_taps <= 2) { in dce60_setup_scaling_configuration()
209 int taps, in program_multi_taps_filter() argument
393 if (taps == 4) in get_filter_coeffs_16p()
1143 uint32_t taps; in decide_taps() local
1148 taps = in_taps; in decide_taps()
1150 taps = 4; in decide_taps()
1154 taps /= 2; in decide_taps()
1155 if (taps < 2) in decide_taps()
1156 taps = 2; in decide_taps()
[all …]
/drivers/gpu/drm/amd/display/dc/dpp/dcn201/
A Ddcn201_dpp.c220 scl_data->taps.h_taps = 8; in dpp201_get_optimal_number_of_taps()
222 scl_data->taps.h_taps = 4; in dpp201_get_optimal_number_of_taps()
228 scl_data->taps.v_taps = 8; in dpp201_get_optimal_number_of_taps()
230 scl_data->taps.v_taps = 4; in dpp201_get_optimal_number_of_taps()
235 scl_data->taps.v_taps_c = 4; in dpp201_get_optimal_number_of_taps()
237 scl_data->taps.v_taps_c = 2; in dpp201_get_optimal_number_of_taps()
242 scl_data->taps.h_taps_c = 4; in dpp201_get_optimal_number_of_taps()
244 scl_data->taps.h_taps_c = 2; in dpp201_get_optimal_number_of_taps()
253 scl_data->taps.h_taps = 1; in dpp201_get_optimal_number_of_taps()
255 scl_data->taps.v_taps = 1; in dpp201_get_optimal_number_of_taps()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_dwb_scl.c651 if (taps == 12) in wbscl_get_filter_coeffs_16p()
657 else if (taps == 9) in wbscl_get_filter_coeffs_16p()
659 else if (taps == 8) in wbscl_get_filter_coeffs_16p()
661 else if (taps == 7) in wbscl_get_filter_coeffs_16p()
663 else if (taps == 6) in wbscl_get_filter_coeffs_16p()
665 else if (taps == 5) in wbscl_get_filter_coeffs_16p()
667 else if (taps == 4) in wbscl_get_filter_coeffs_16p()
669 else if (taps == 3) in wbscl_get_filter_coeffs_16p()
671 else if (taps == 2) in wbscl_get_filter_coeffs_16p()
673 else if (taps == 1) in wbscl_get_filter_coeffs_16p()
[all …]
/drivers/gpu/drm/amd/display/dc/dce110/
A Ddce110_transform_v.c176 if (data->taps.h_taps + data->taps.v_taps > 2) { in setup_scaling_configuration()
185 if (data->taps.h_taps_c + data->taps.v_taps_c > 2) { in setup_scaling_configuration()
284 int taps, in program_multi_taps_filter() argument
291 int taps_pairs = (taps + 1) / 2; in program_multi_taps_filter()
490 if (taps == 4) in get_filter_coeffs_64p()
492 else if (taps == 2) in get_filter_coeffs_64p()
494 else if (taps == 1) in get_filter_coeffs_64p()
571 data->taps.v_taps, in dce110_xfmv_set_scaler()
576 data->taps.v_taps_c, in dce110_xfmv_set_scaler()
583 data->taps.h_taps, in dce110_xfmv_set_scaler()
[all …]
/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
A Ddcn401_dpp_dscl.c219 if (taps == 8) in dpp401_dscl_get_filter_coeffs_64p()
221 else if (taps == 7) in dpp401_dscl_get_filter_coeffs_64p()
223 else if (taps == 6) in dpp401_dscl_get_filter_coeffs_64p()
225 else if (taps == 5) in dpp401_dscl_get_filter_coeffs_64p()
227 else if (taps == 4) in dpp401_dscl_get_filter_coeffs_64p()
229 else if (taps == 3) in dpp401_dscl_get_filter_coeffs_64p()
231 else if (taps == 2) in dpp401_dscl_get_filter_coeffs_64p()
233 else if (taps == 1) in dpp401_dscl_get_filter_coeffs_64p()
244 uint32_t taps, in dpp401_dscl_set_scaler_filter() argument
320 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1); in dpp401_dscl_set_scl_filter()
[all …]
/drivers/mmc/host/
A Dsdhci-of-aspeed.c144 const struct aspeed_sdhci_tap_param *taps) in aspeed_sdc_set_phase_taps() argument
151 reg = aspeed_sdc_set_phase_tap(&desc->in, taps->in, taps->valid, reg); in aspeed_sdc_set_phase_taps()
152 reg = aspeed_sdc_set_phase_tap(&desc->out, taps->out, taps->valid, reg); in aspeed_sdc_set_phase_taps()
201 struct aspeed_sdhci_tap_param *taps) in aspeed_sdhci_phases_to_taps() argument
203 taps->valid = phases->valid; in aspeed_sdhci_phases_to_taps()
208 taps->in = aspeed_sdhci_phase_to_tap(dev, rate, phases->in_deg); in aspeed_sdhci_phases_to_taps()
209 taps->out = aspeed_sdhci_phase_to_tap(dev, rate, phases->out_deg); in aspeed_sdhci_phases_to_taps()
215 struct aspeed_sdhci_tap_param _taps = {0}, *taps = &_taps; in aspeed_sdhci_configure_phase() local
227 aspeed_sdhci_phases_to_taps(dev, rate, params, taps); in aspeed_sdhci_configure_phase()
231 taps->in & ASPEED_SDHCI_NR_TAPS, in aspeed_sdhci_configure_phase()
[all …]
A Drenesas_sdhi_core.c649 if (!test_bit(i, priv->taps)) in renesas_sdhi_select_tuning()
650 clear_bit(i + offset, priv->taps); in renesas_sdhi_select_tuning()
660 if (bitmap_full(priv->taps, taps_size)) { in renesas_sdhi_select_tuning()
664 bitmap = priv->taps; in renesas_sdhi_select_tuning()
712 bitmap_zero(priv->taps, priv->tap_num * 2); in renesas_sdhi_execute_tuning()
723 set_bit(i, priv->taps); in renesas_sdhi_execute_tuning()
1242 const struct renesas_sdhi_scc *taps = of_data->taps; in renesas_sdhi_probe() local
1247 if (taps[i].clk_rate == 0 || in renesas_sdhi_probe()
1249 priv->scc_tappos = taps->tap; in renesas_sdhi_probe()
1251 taps->tap_hs400_4tap : in renesas_sdhi_probe()
[all …]
A Drenesas_sdhi.h34 struct renesas_sdhi_scc *taps; member
91 DECLARE_BITMAP(taps, BITS_PER_LONG);
A Drenesas_sdhi_internal_dmac.c101 .taps = rcar_gen3_scc_taps,
116 .taps = rcar_gen3_scc_taps,
132 .taps = rcar_gen3_scc_taps,
/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
A Ddcn30_dpp.c437 scl_data->taps.h_taps = 4; in dpp3_get_optimal_number_of_taps()
444 scl_data->taps.v_taps = 4; in dpp3_get_optimal_number_of_taps()
451 scl_data->taps.v_taps_c = 4; in dpp3_get_optimal_number_of_taps()
458 scl_data->taps.h_taps_c = 4; in dpp3_get_optimal_number_of_taps()
500 if (scl_data->taps.v_taps > max_taps_y) in dpp3_get_optimal_number_of_taps()
501 scl_data->taps.v_taps = max_taps_y; in dpp3_get_optimal_number_of_taps()
504 scl_data->taps.v_taps_c = max_taps_c; in dpp3_get_optimal_number_of_taps()
508 scl_data->taps.h_taps = 1; in dpp3_get_optimal_number_of_taps()
510 scl_data->taps.v_taps = 1; in dpp3_get_optimal_number_of_taps()
512 scl_data->taps.h_taps_c = 1; in dpp3_get_optimal_number_of_taps()
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_translation_helper.c830 temp_pipe->plane_res.scl_data.taps = pipe->plane_res.scl_data.taps; in get_scaler_data_for_plane()
897 if (!scaler_data->taps.h_taps) { in populate_dml21_plane_config_from_plane_state()
907 if ((scaler_data->taps.h_taps > 1) || (scaler_data->taps.v_taps > 1) || in populate_dml21_plane_config_from_plane_state()
908 (scaler_data->taps.h_taps_c > 1) || (scaler_data->taps.v_taps_c > 1)) in populate_dml21_plane_config_from_plane_state()
930 if (!scaler_data->taps.h_taps) { in populate_dml21_plane_config_from_plane_state()
934 plane->composition.scaler_info.plane0.h_taps = scaler_data->taps.h_taps; in populate_dml21_plane_config_from_plane_state()
935 plane->composition.scaler_info.plane1.h_taps = scaler_data->taps.h_taps_c; in populate_dml21_plane_config_from_plane_state()
937 if (!scaler_data->taps.v_taps) { in populate_dml21_plane_config_from_plane_state()
941 plane->composition.scaler_info.plane0.v_taps = scaler_data->taps.v_taps; in populate_dml21_plane_config_from_plane_state()
942 plane->composition.scaler_info.plane1.v_taps = scaler_data->taps.v_taps_c; in populate_dml21_plane_config_from_plane_state()
/drivers/net/
A Dtap.c92 rcu_assign_pointer(tap->taps[tap->numvtaps], q); in tap_enable_queue()
109 rcu_assign_pointer(tap->taps[tap->numvtaps], q); in tap_set_queue()
138 nq = rtnl_dereference(tap->taps[tap->numvtaps - 1]); in tap_disable_queue()
141 rcu_assign_pointer(tap->taps[index], nq); in tap_disable_queue()
142 RCU_INIT_POINTER(tap->taps[tap->numvtaps - 1], NULL); in tap_disable_queue()
210 queue = rcu_dereference(tap->taps[rxq % numvtaps]); in tap_get_queue()
220 queue = rcu_dereference(tap->taps[rxq]); in tap_get_queue()
225 queue = rcu_dereference(tap->taps[0]); in tap_get_queue()
/drivers/gpu/drm/amd/display/dc/
A Ddc_spl_translate.c226 populate_taps_from_spltaps(&pipe_ctx->plane_res.scl_data.taps, &spl_out->dscl_prog_data->taps); in translate_SPL_out_params_to_pipe_ctx()
/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calcs.c398 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; in pipe_ctx_to_e2e_pipe_params()
404 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps; in pipe_ctx_to_e2e_pipe_params()
405 input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c; in pipe_ctx_to_e2e_pipe_params()
406 input->scale_taps.htaps_c = pipe->plane_res.scl_data.taps.h_taps_c; in pipe_ctx_to_e2e_pipe_params()
1012 v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps; in dcn_validate_bandwidth()
1013 v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps; in dcn_validate_bandwidth()
1014 v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c; in dcn_validate_bandwidth()
1015 v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c; in dcn_validate_bandwidth()
/drivers/gpu/drm/imx/dcss/
A Ddcss-scaler.c180 int taps; in dcss_scaler_gaussian_filter() local
189 taps = use_5_taps ? PSC_NUM_TAPS_RGBA : PSC_NUM_TAPS; in dcss_scaler_gaussian_filter()
190 mid = (PSC_NUM_PHASES * taps) / 2 - 1; in dcss_scaler_gaussian_filter()

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