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Searched refs:tegra_clk_register_periph_gate (Results 1 – 9 of 9) sorted by relevance

/drivers/clk/tegra/
A Dclk-tegra20.c741 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler", in tegra20_audio_clk_init()
790 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0", in tegra20_periph_clk_init()
805 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, in tegra20_periph_clk_init()
811 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70, in tegra20_periph_clk_init()
828 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_mux", 0, in tegra20_periph_clk_init()
833 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_mux", 0, in tegra20_periph_clk_init()
A Dclk-periph-gate.c136 struct clk *tegra_clk_register_periph_gate(const char *name, in tegra_clk_register_periph_gate() function
A Dclk-tegra-audio.c241 clk = tegra_clk_register_periph_gate(data->gate_name, in tegra_audio_clk_init()
A Dclk-tegra114.c1040 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base, in tegra114_periph_clk_init()
1044 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base, in tegra114_periph_clk_init()
1059 clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base, in tegra114_periph_clk_init()
A Dclk-tegra30.c1007 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base, in tegra30_periph_clk_init()
1012 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, in tegra30_periph_clk_init()
1017 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72, in tegra30_periph_clk_init()
A Dclk-tegra124.c1043 clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0, in tegra124_periph_clk_init()
1048 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0, in tegra124_periph_clk_init()
A Dclk.h583 struct clk *tegra_clk_register_periph_gate(const char *name,
A Dclk-tegra-periph.c903 clk = tegra_clk_register_periph_gate(data->name, in gate_clk_init()
A Dclk-tegra210.c3119 clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0, in tegra210_periph_clk_init()
3125 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0, in tegra210_periph_clk_init()

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