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Searched refs:tegra_dc_writel (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/tegra/
A Ddc.c54 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
56 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
1695 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL); in tegra_dc_show_crc()
1789 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
1801 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
1845 tegra_dc_writel(dc, value, DC_DISP_ACTIVE); in tegra_dc_set_timings()
2196 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); in tegra_crtc_atomic_enable()
2210 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_crtc_atomic_enable()
2216 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); in tegra_crtc_atomic_enable()
2237 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_crtc_atomic_enable()
[all …]
A Drgb.c88 tegra_dc_writel(dc, table[i].value, table[i].offset); in tegra_dc_write_regs()
110 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS); in tegra_rgb_encoder_enable()
125 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1)); in tegra_rgb_encoder_enable()
130 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL); in tegra_rgb_encoder_enable()
A Dhub.c110 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
201 tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL); in tegra_shared_plane_update()
221 tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL); in tegra_shared_plane_activate()
293 tegra_dc_writel(dc, value, offset); in tegra_shared_plane_set_owner()
897 tegra_dc_writel(dc, value, DC_CMD_IHUB_COMMON_MISC_CTL); in tegra_display_hub_update()
901 tegra_dc_writel(dc, value, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER); in tegra_display_hub_update()
903 tegra_dc_writel(dc, COMMON_UPDATE, DC_CMD_STATE_CONTROL); in tegra_display_hub_update()
905 tegra_dc_writel(dc, COMMON_ACTREQ, DC_CMD_STATE_CONTROL); in tegra_display_hub_update()
A Dhdmi.c1181 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_hdmi_encoder_disable()
1259 tegra_dc_writel(dc, VSYNC_H_POSITION(1), in tegra_hdmi_encoder_enable()
1261 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888, in tegra_hdmi_encoder_enable()
1267 tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_hdmi_encoder_enable()
1271 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); in tegra_hdmi_encoder_enable()
1274 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); in tegra_hdmi_encoder_enable()
1418 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_hdmi_encoder_enable()
A Dsor.c2231 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
2456 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); in tegra_sor_hdmi_enable()
2459 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); in tegra_sor_hdmi_enable()
2463 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
2553 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); in tegra_sor_hdmi_enable()
2583 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2628 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()
2634 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2684 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_disable()
2925 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_enable()
A Ddc.h119 static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value, in tegra_dc_writel() function
A Ddsi.c862 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_dsi_encoder_disable()
949 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_dsi_encoder_enable()

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