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Searched refs:tg (Results 1 – 25 of 93) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dtiming_generator.h222 bool (*enable_crtc)(struct timing_generator *tg);
228 void (*get_position)(struct timing_generator *tg,
233 struct timing_generator *tg,
247 void (*set_blank)(struct timing_generator *tg,
249 bool (*is_blanked)(struct timing_generator *tg);
252 void (*set_colors)(struct timing_generator *tg,
260 void (*unlock)(struct timing_generator *tg);
261 void (*lock)(struct timing_generator *tg);
282 struct timing_generator *tg,
301 void (*tg_init)(struct timing_generator *tg);
[all …]
/drivers/gpu/drm/amd/display/dc/dce110/
A Ddce110_timing_generator.h117 #define DCE110TG_FROM_TG(tg)\ argument
128 struct timing_generator *tg,
136 struct timing_generator *tg,
154 struct timing_generator *tg,
170 struct timing_generator *tg,
179 struct timing_generator *tg,
185 struct timing_generator *tg,
202 struct timing_generator *tg,
208 struct timing_generator *tg,
212 struct timing_generator *tg,
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A Ddce110_timing_generator.c66 struct timing_generator *tg, in dce110_timing_generator_apply_front_porch_workaround() argument
146 result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true); in dce110_timing_generator_enable_crtc()
217 tg->funcs->wait_for_vblank(tg);
218 tg->funcs->wait_for_vactive(tg);
238 result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, false); in dce110_timing_generator_disable_crtc()
271 dm_write_reg(tg->ctx, in program_horz_count_by_2()
342 result = tg->bp->funcs->program_crtc_timing(tg->bp, &bp_params); in dce110_timing_generator_program_timing_generator()
590 tg, &position); in dce110_timing_generator_get_crtc_scanoutpos()
1399 tg->funcs->get_position(tg, &position1); in dce110_timing_generator_is_counter_moving()
1400 tg->funcs->get_position(tg, &position2); in dce110_timing_generator_is_counter_moving()
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A Ddce110_timing_generator_v.c42 tg->ctx->logger
64 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
74 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
84 value = dm_read_reg(tg->ctx, in dce110_timing_generator_v_disable_crtc()
90 dm_write_reg(tg->ctx, in dce110_timing_generator_v_disable_crtc()
140 struct timing_generator *tg) in dce110_timing_generator_v_is_in_vertical_blank() argument
242 struct timing_generator *tg, in dce110_timing_generator_v_program_blanking() argument
384 struct timing_generator *tg, in dce110_timing_generator_v_enable_advanced_request() argument
478 struct timing_generator *tg, in dce110_timing_generator_v_set_overscan_color_black() argument
614 struct timing_generator *tg) in dce110_timing_generator_v_did_triggered_reset_occur() argument
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/drivers/gpu/drm/amd/display/dc/dce120/
A Ddce120_timing_generator.c91 tg->ctx, in dce120_timing_generator_is_in_vertical_blank()
114 tg, in dce120_timing_generator_validate_timing()
174 tg->ctx, in dce120_timing_generator_get_vblank_counter()
190 tg->ctx, in dce120_timing_generator_get_crtc_position()
217 if (!tg->funcs->is_counter_moving(tg)) { in dce120_timing_generator_wait_for_vblank()
224 if (!tg->funcs->is_counter_moving(tg)) { in dce120_timing_generator_wait_for_vblank()
235 if (!tg->funcs->is_counter_moving(tg)) { in dce120_timing_generator_wait_for_vactive()
375 tg->ctx, in dce120_timing_generator_did_triggered_reset_occur()
529 tg->ctx, in dce120_timing_generator_set_overscan_color_black()
676 tg->ctx, in dce120_tg_program_blank_color()
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/drivers/gpu/drm/amd/display/dc/dce60/
A Ddce60_timing_generator.c91 + DCE110TG_FROM_TG(tg)->offsets.dmif; in program_pix_dur()
92 uint32_t value = dm_read_reg(tg->ctx, addr); in program_pix_dur()
105 dm_write_reg(tg->ctx, addr, value); in program_pix_dur()
119 program_pix_dur(tg, timing->pix_clk_100hz); in program_timing()
125 struct timing_generator *tg, in dce60_timing_generator_enable_advanced_request() argument
131 uint32_t value = dm_read_reg(tg->ctx, addr); in dce60_timing_generator_enable_advanced_request()
134 uint32_t value2 = dm_read_reg(tg->ctx, addr2); in dce60_timing_generator_enable_advanced_request()
175 dm_write_reg(tg->ctx, addr, value); in dce60_timing_generator_enable_advanced_request()
176 dm_write_reg(tg->ctx, addr2, value2); in dce60_timing_generator_enable_advanced_request()
187 value = dm_read_reg(tg->ctx, addr); in dce60_is_tg_enabled()
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/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
A Ddcn10_hwseq.c124 if (tg->funcs->is_tg_enabled && !tg->funcs->is_tg_enabled(tg)) in dcn10_wait_for_pipe_update_if_needed()
200 if (tg->funcs->is_tg_enabled && !tg->funcs->is_tg_enabled(tg)) in dcn10_set_wait_for_update_needed_for_pipe()
231 tg = pipe_ctx->stream_res.tg; in dcn10_lock_all_pipes()
240 !tg->funcs->is_tg_enabled(tg) || in dcn10_lock_all_pipes()
1566 tg->funcs->lock(tg); in dcn10_init_pipes()
1568 tg->funcs->lock(tg); in dcn10_init_pipes()
1622 tg->funcs->tg_init(tg); in dcn10_init_pipes()
1634 pipe_ctx->stream_res.tg = tg; in dcn10_init_pipes()
1652 tg->funcs->unlock(tg); in dcn10_init_pipes()
1661 tg->funcs->init_odm(tg); in dcn10_init_pipes()
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/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
A Ddcn201_hwseq.c180 tg->funcs->get_otg_active_size(tg, in dcn201_init_blank()
185 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); in dcn201_init_blank()
275 if (tg->funcs->is_tg_enabled(tg)) { in dcn201_init_hw()
283 if (tg->funcs->is_tg_enabled(tg)) in dcn201_init_hw()
284 tg->funcs->lock(tg); in dcn201_init_hw()
310 pipe_ctx->stream_res.tg = tg; in dcn201_init_hw()
336 if (tg->funcs->is_tg_enabled(tg)) in dcn201_init_hw()
337 tg->funcs->unlock(tg); in dcn201_init_hw()
352 tg->funcs->tg_init(tg); in dcn201_init_hw()
547 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); in dcn201_pipe_control_lock()
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/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
A Ddcn35_hwseq.c225 if (tg->funcs->is_tg_enabled(tg) && tg->funcs->get_optc_source) { in dcn35_init_hw()
734 tg->funcs->lock(tg); in dcn35_init_pipes()
736 tg->funcs->lock(tg); in dcn35_init_pipes()
737 tg->funcs->set_blank(tg, true); in dcn35_init_pipes()
790 tg->funcs->tg_init(tg); in dcn35_init_pipes()
802 pipe_ctx->stream_res.tg = tg; in dcn35_init_pipes()
819 if (tg->funcs->is_tg_enabled(tg)) in dcn35_init_pipes()
820 tg->funcs->unlock(tg); in dcn35_init_pipes()
829 tg->funcs->init_odm(tg); in dcn35_init_pipes()
832 tg->funcs->tg_init(tg); in dcn35_init_pipes()
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/drivers/gpu/drm/amd/display/dc/dce80/
A Ddce80_timing_generator.c87 static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz) in program_pix_dur() argument
91 + DCE110TG_FROM_TG(tg)->offsets.dmif; in program_pix_dur()
92 uint32_t value = dm_read_reg(tg->ctx, addr); in program_pix_dur()
105 dm_write_reg(tg->ctx, addr, value); in program_pix_dur()
108 static void dce80_timing_generator_program_timing(struct timing_generator *tg, in dce80_timing_generator_program_timing() argument
119 program_pix_dur(tg, timing->pix_clk_100hz); in dce80_timing_generator_program_timing()
121 dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, 0, use_vbios); in dce80_timing_generator_program_timing()
125 struct timing_generator *tg, in dce80_timing_generator_enable_advanced_request() argument
129 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce80_timing_generator_enable_advanced_request()
131 uint32_t value = dm_read_reg(tg->ctx, addr); in dce80_timing_generator_enable_advanced_request()
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/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
A Ddcn20_hwseq.c422 tg->funcs->get_otg_active_size(tg, in dcn20_init_blank()
757 if (tg && tg->funcs->disable_phantom_crtc) in dcn20_disable_plane()
758 tg->funcs->disable_phantom_crtc(tg); in dcn20_disable_plane()
2101 tg->funcs->enable_crtc(tg); in dcn20_program_front_end_for_ctx()
3151 if (tg->funcs->is_tg_enabled(tg)) in dcn20_fpga_init_hw()
3158 if (tg->funcs->is_tg_enabled(tg)) in dcn20_fpga_init_hw()
3159 tg->funcs->lock(tg); in dcn20_fpga_init_hw()
3185 pipe_ctx->stream_res.tg = tg; in dcn20_fpga_init_hw()
3213 if (tg->funcs->is_tg_enabled(tg)) in dcn20_fpga_init_hw()
3214 tg->funcs->unlock(tg); in dcn20_fpga_init_hw()
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/drivers/gpu/drm/amd/display/dc/hwss/dce110/
A Ddce110_hwseq.c672 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dce110_enable_stream() local
690 tg->funcs->set_early_control(tg, early_control); in dce110_enable_stream()
1155 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dce110_disable_stream() local
1800 tg->funcs->disable_vga(tg); in disable_vga_and_power_gate_all_controllers()
2139 if ((tg != NULL) && tg->funcs) { in set_drr()
2689 if (!tg->funcs->is_counter_moving(tg)) { in wait_for_reset_trigger_to_occur()
2694 if (tg->funcs->did_triggered_reset_occur(tg)) { in wait_for_reset_trigger_to_occur()
2703 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); in wait_for_reset_trigger_to_occur()
2704 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); in wait_for_reset_trigger_to_occur()
2844 tg->funcs->disable_vga(tg); in dce110_init_hw()
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/drivers/gpu/drm/amd/display/dc/link/accessories/
A Dlink_dp_cts.c96 pipes[i]->stream_res.tg->funcs->disable_crtc(pipes[i]->stream_res.tg); in dp_retrain_link_dp_test()
138 pipes[i]->stream_res.tg->funcs->enable_crtc(pipes[i]->stream_res.tg); in dp_retrain_link_dp_test()
500 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, in set_crtc_test_pattern()
539 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, in set_crtc_test_pattern()
883 pipe_ctx->stream_res.tg); in dp_set_test_pattern()
886 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg); in dp_set_test_pattern()
909 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg); in dp_set_test_pattern()
910 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, in dp_set_test_pattern()
912 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, in dp_set_test_pattern()
914 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, in dp_set_test_pattern()
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/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
A Ddcn314_hwseq.c128 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, in update_dsc_on_stream()
134 pipe_ctx->stream_res.tg->funcs->set_dsc_config( in update_dsc_on_stream()
135 pipe_ctx->stream_res.tg, in update_dsc_on_stream()
185 pipe_ctx->stream_res.tg->funcs->set_odm_combine( in dcn314_update_odm()
186 pipe_ctx->stream_res.tg, in dcn314_update_odm()
190 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( in dcn314_update_odm()
191 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); in dcn314_update_odm()
419 pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg); in dcn314_resync_fifo_dccg_dio()
445 pipe->stream_res.tg->funcs->set_odm_combine( in dcn314_resync_fifo_dccg_dio()
446 pipe->stream_res.tg, in dcn314_resync_fifo_dccg_dio()
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/drivers/gpu/drm/amd/display/dc/hwss/dce/
A Ddce_hwseq.c56 if (lock && pipe->stream_res.tg->funcs->is_blanked && in dce_pipe_control_lock()
57 pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg)) in dce_pipe_control_lock()
60 val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], in dce_pipe_control_lock()
71 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
82 uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]); in dce_pipe_control_lock()
83 REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value); in dce_pipe_control_lock()
/drivers/iio/chemical/
A Dsgp40.c172 struct sgp40_tg_measure tg = {.command = {0x26, 0x0F}}; in sgp40_measure_resistance_raw() local
179 tg.rht_ticks = cpu_to_be16(ticks16); in sgp40_measure_resistance_raw()
180 tg.rht_crc = crc8(sgp40_crc8_table, (u8 *)&tg.rht_ticks, 2, SGP40_CRC8_INIT); in sgp40_measure_resistance_raw()
184 tg.temp_ticks = cpu_to_be16(ticks16); in sgp40_measure_resistance_raw()
185 tg.temp_crc = crc8(sgp40_crc8_table, (u8 *)&tg.temp_ticks, 2, SGP40_CRC8_INIT); in sgp40_measure_resistance_raw()
189 ret = i2c_master_send(client, (const char *)&tg, sizeof(tg)); in sgp40_measure_resistance_raw()
190 if (ret != sizeof(tg)) { in sgp40_measure_resistance_raw()
191 dev_warn(data->dev, "i2c_master_send ret: %d sizeof: %zu\n", ret, sizeof(tg)); in sgp40_measure_resistance_raw()
/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
A Ddcn401_hwseq.c936 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn401_enable_stream() local
988 tg->funcs->set_early_control(tg, early_control); in dcn401_enable_stream()
1682 tg = pipe->stream_res.tg; in dcn401_interdependent_update_lock()
1685 !tg->funcs->is_tg_enabled(tg) || in dcn401_interdependent_update_lock()
1694 tg = pipe->stream_res.tg; in dcn401_interdependent_update_lock()
1697 !tg->funcs->is_tg_enabled(tg) || in dcn401_interdependent_update_lock()
1716 tg = pipe->stream_res.tg; in dcn401_interdependent_update_lock()
1718 !tg->funcs->is_tg_enabled(tg) || in dcn401_interdependent_update_lock()
2140 tg->funcs->enable_crtc(tg); in dcn401_program_front_end_for_ctx()
2295 struct timing_generator *tg = pipe->stream_res.tg; in dcn401_post_unlock_program_front_end() local
[all …]
/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
A Ddcn31_hwseq.c199 if (tg) { in dcn31_init_hw()
200 if (tg->funcs->is_tg_enabled(tg) && tg->funcs->get_optc_source) { in dcn31_init_hw()
201 tg->funcs->get_optc_source(tg, &num_opps, in dcn31_init_hw()
539 pipe_ctx->stream_res.tg->funcs->set_dsc_config( in dcn31_reset_back_end_for_pipe()
540 pipe_ctx->stream_res.tg, in dcn31_reset_back_end_for_pipe()
543 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); in dcn31_reset_back_end_for_pipe()
545 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); in dcn31_reset_back_end_for_pipe()
666 pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(pipe_ctx[i]->stream_res.tg, in dcn31_set_static_screen_control()
698 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn31_set_backlight_level() local
702 if (!abm || !tg || !panel_cntl) in dcn31_set_backlight_level()
[all …]
/drivers/gpu/drm/amd/display/dc/hwss/dcn21/
A Ddcn21_hwseq.c182 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_abm_immediate_disable()
215 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn21_set_pipe() local
220 if (!abm || !tg || !panel_cntl) in dcn21_set_pipe()
223 otg_inst = tg->inst; in dcn21_set_pipe()
249 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn21_set_backlight_level() local
255 if (!abm || !tg || !panel_cntl) in dcn21_set_backlight_level()
258 otg_inst = tg->inst; in dcn21_set_backlight_level()
/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
A Ddcn30_hwseq.c840 if (enable && pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) { in dcn30_set_avmute()
841 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); in dcn30_set_avmute()
842 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); in dcn30_set_avmute()
843 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); in dcn30_set_avmute()
844 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); in dcn30_set_avmute()
845 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); in dcn30_set_avmute()
1207 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn30_wait_for_all_pending_updates() local
1211 if (tg && tg->funcs->is_tg_enabled(tg)) { in dcn30_wait_for_all_pending_updates()
1216 pending_updates |= tg->funcs->get_optc_double_buffer_pending(tg); in dcn30_wait_for_all_pending_updates()
1219 pending_updates |= tg->funcs->get_otg_double_buffer_pending(tg); in dcn30_wait_for_all_pending_updates()
[all …]
/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
A Ddcn32_hwseq.c409 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK); in dcn32_subvp_pipe_control_lock()
1083 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, in dcn32_update_dsc_on_stream()
1090 pipe_ctx->stream_res.tg, in dcn32_update_dsc_on_stream()
1262 pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg); in dcn32_resync_fifo_dccg_dio()
1289 pipe->stream_res.tg, in dcn32_resync_fifo_dccg_dio()
1293 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); in dcn32_resync_fifo_dccg_dio()
1647 tg->funcs->get_otg_active_size(tg, in dcn32_init_blank()
1652 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); in dcn32_init_blank()
1757 if (cur_pipe->stream_res.tg == new_pipe->stream_res.tg) in dcn32_is_pipe_topology_transition_seamless()
1825 tg = pipe->stream_res.tg; in dcn32_interdependent_update_lock()
[all …]
/drivers/firmware/efi/libstub/
A Darm64.c60 u64 tg; in check_platform_features() local
74 tg = (read_cpuid(ID_AA64MMFR0_EL1) >> ID_AA64MMFR0_EL1_TGRAN_SHIFT) & 0xf; in check_platform_features()
75 if (tg < ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN || tg > ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX) { in check_platform_features()
/drivers/media/platform/qcom/camss/
A Dcamss-csid-4-1.c49 struct csid_testgen_config *tg = &csid->testgen; in csid_configure_stream() local
59 if (tg->enabled) { in csid_configure_stream()
86 val = tg->mode - 1; in csid_configure_stream()
121 if (tg->enabled) { in csid_configure_stream()
126 if (tg->enabled) { in csid_configure_stream()
A Dcamss-csid-4-7.c48 struct csid_testgen_config *tg = &csid->testgen; in csid_configure_stream() local
60 if (tg->enabled) { in csid_configure_stream()
87 val = tg->mode - 1; in csid_configure_stream()
133 if (tg->enabled) { in csid_configure_stream()
138 if (tg->enabled) { in csid_configure_stream()
/drivers/hwtracing/coresight/
A Dcoresight-cti-platform.c317 struct cti_trig_grp *tg = NULL; in cti_plat_process_filter_sigs() local
328 tg = kzalloc(sizeof(*tg), GFP_KERNEL); in cti_plat_process_filter_sigs()
329 if (!tg) in cti_plat_process_filter_sigs()
332 err = cti_plat_read_trig_group(tg, fwnode, CTI_DT_FILTER_OUT_SIGS); in cti_plat_process_filter_sigs()
334 drvdata->config.trig_out_filter |= tg->used_mask; in cti_plat_process_filter_sigs()
336 kfree(tg); in cti_plat_process_filter_sigs()

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