| /drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| A D | dcn201_resource.c | 761 struct optc *tgn10 = in dcn201_timing_generator_create() local
764 if (!tgn10) in dcn201_timing_generator_create()
767 tgn10->base.inst = instance; in dcn201_timing_generator_create()
768 tgn10->base.ctx = ctx; in dcn201_timing_generator_create()
770 tgn10->tg_regs = &tg_regs[instance]; in dcn201_timing_generator_create()
771 tgn10->tg_shift = &tg_shift; in dcn201_timing_generator_create()
772 tgn10->tg_mask = &tg_mask; in dcn201_timing_generator_create()
774 dcn201_timing_generator_init(tgn10); in dcn201_timing_generator_create()
776 return &tgn10->base; in dcn201_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| A D | dcn302_resource.c | 605 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); in dcn302_timing_generator_create() local
607 if (!tgn10) in dcn302_timing_generator_create()
610 tgn10->base.inst = instance; in dcn302_timing_generator_create()
611 tgn10->base.ctx = ctx; in dcn302_timing_generator_create()
613 tgn10->tg_regs = &optc_regs[instance]; in dcn302_timing_generator_create()
614 tgn10->tg_shift = &optc_shift; in dcn302_timing_generator_create()
615 tgn10->tg_mask = &optc_mask; in dcn302_timing_generator_create()
617 dcn30_timing_generator_init(tgn10); in dcn302_timing_generator_create()
619 return &tgn10->base; in dcn302_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| A D | dcn303_resource.c | 578 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); in dcn303_timing_generator_create() local
580 if (!tgn10) in dcn303_timing_generator_create()
583 tgn10->base.inst = instance; in dcn303_timing_generator_create()
584 tgn10->base.ctx = ctx; in dcn303_timing_generator_create()
586 tgn10->tg_regs = &optc_regs[instance]; in dcn303_timing_generator_create()
587 tgn10->tg_shift = &optc_shift; in dcn303_timing_generator_create()
588 tgn10->tg_mask = &optc_mask; in dcn303_timing_generator_create()
590 dcn30_timing_generator_init(tgn10); in dcn303_timing_generator_create()
592 return &tgn10->base; in dcn303_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| A D | dcn10_resource.c | 705 struct optc *tgn10 = in dcn10_timing_generator_create() local
708 if (!tgn10) in dcn10_timing_generator_create()
711 tgn10->base.inst = instance; in dcn10_timing_generator_create()
712 tgn10->base.ctx = ctx; in dcn10_timing_generator_create()
714 tgn10->tg_regs = &tg_regs[instance]; in dcn10_timing_generator_create()
715 tgn10->tg_shift = &tg_shift; in dcn10_timing_generator_create()
716 tgn10->tg_mask = &tg_mask; in dcn10_timing_generator_create()
718 dcn10_timing_generator_init(tgn10); in dcn10_timing_generator_create()
720 return &tgn10->base; in dcn10_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| A D | dcn21_resource.c | 1044 struct optc *tgn10 = in dcn21_timing_generator_create() local
1047 if (!tgn10) in dcn21_timing_generator_create()
1050 tgn10->base.inst = instance; in dcn21_timing_generator_create()
1051 tgn10->base.ctx = ctx; in dcn21_timing_generator_create()
1053 tgn10->tg_regs = &tg_regs[instance]; in dcn21_timing_generator_create()
1054 tgn10->tg_shift = &tg_shift; in dcn21_timing_generator_create()
1055 tgn10->tg_mask = &tg_mask; in dcn21_timing_generator_create()
1057 dcn20_timing_generator_init(tgn10); in dcn21_timing_generator_create()
1059 return &tgn10->base; in dcn21_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| A D | dcn301_resource.c | 848 struct optc *tgn10 = in dcn301_timing_generator_create() local
851 if (!tgn10) in dcn301_timing_generator_create()
854 tgn10->base.inst = instance; in dcn301_timing_generator_create()
855 tgn10->base.ctx = ctx; in dcn301_timing_generator_create()
857 tgn10->tg_regs = &optc_regs[instance]; in dcn301_timing_generator_create()
858 tgn10->tg_shift = &optc_shift; in dcn301_timing_generator_create()
859 tgn10->tg_mask = &optc_mask; in dcn301_timing_generator_create()
861 dcn301_timing_generator_init(tgn10); in dcn301_timing_generator_create()
863 return &tgn10->base; in dcn301_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| A D | dcn316_resource.c | 1050 struct optc *tgn10 = in dcn31_timing_generator_create() local
1053 if (!tgn10) in dcn31_timing_generator_create()
1056 tgn10->base.inst = instance; in dcn31_timing_generator_create()
1057 tgn10->base.ctx = ctx; in dcn31_timing_generator_create()
1059 tgn10->tg_regs = &optc_regs[instance]; in dcn31_timing_generator_create()
1060 tgn10->tg_shift = &optc_shift; in dcn31_timing_generator_create()
1061 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
1063 dcn31_timing_generator_init(tgn10); in dcn31_timing_generator_create()
1065 return &tgn10->base; in dcn31_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| A D | dcn314_resource.c | 1115 struct optc *tgn10 = in dcn31_timing_generator_create() local
1118 if (!tgn10) in dcn31_timing_generator_create()
1121 tgn10->base.inst = instance; in dcn31_timing_generator_create()
1122 tgn10->base.ctx = ctx; in dcn31_timing_generator_create()
1124 tgn10->tg_regs = &optc_regs[instance]; in dcn31_timing_generator_create()
1125 tgn10->tg_shift = &optc_shift; in dcn31_timing_generator_create()
1126 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
1128 dcn314_timing_generator_init(tgn10); in dcn31_timing_generator_create()
1130 return &tgn10->base; in dcn31_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| A D | dcn31_resource.c | 1058 struct optc *tgn10 = in dcn31_timing_generator_create() local
1061 if (!tgn10) in dcn31_timing_generator_create()
1064 tgn10->base.inst = instance; in dcn31_timing_generator_create()
1065 tgn10->base.ctx = ctx; in dcn31_timing_generator_create()
1067 tgn10->tg_regs = &optc_regs[instance]; in dcn31_timing_generator_create()
1068 tgn10->tg_shift = &optc_shift; in dcn31_timing_generator_create()
1069 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
1071 dcn31_timing_generator_init(tgn10); in dcn31_timing_generator_create()
1073 return &tgn10->base; in dcn31_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| A D | dcn321_resource.c | 993 struct optc *tgn10 = in dcn321_timing_generator_create() local
996 if (!tgn10) in dcn321_timing_generator_create()
1006 tgn10->base.inst = instance; in dcn321_timing_generator_create()
1007 tgn10->base.ctx = ctx; in dcn321_timing_generator_create()
1009 tgn10->tg_regs = &optc_regs[instance]; in dcn321_timing_generator_create()
1010 tgn10->tg_shift = &optc_shift; in dcn321_timing_generator_create()
1011 tgn10->tg_mask = &optc_mask; in dcn321_timing_generator_create()
1013 dcn32_timing_generator_init(tgn10); in dcn321_timing_generator_create()
1015 return &tgn10->base; in dcn321_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| A D | dcn35_resource.c | 1032 struct optc *tgn10 = in dcn35_timing_generator_create() local
1035 if (!tgn10) in dcn35_timing_generator_create()
1045 tgn10->base.inst = instance; in dcn35_timing_generator_create()
1046 tgn10->base.ctx = ctx; in dcn35_timing_generator_create()
1048 tgn10->tg_regs = &optc_regs[instance]; in dcn35_timing_generator_create()
1049 tgn10->tg_shift = &optc_shift; in dcn35_timing_generator_create()
1050 tgn10->tg_mask = &optc_mask; in dcn35_timing_generator_create()
1052 dcn35_timing_generator_init(tgn10); in dcn35_timing_generator_create()
1054 return &tgn10->base; in dcn35_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| A D | dcn315_resource.c | 1056 struct optc *tgn10 = in dcn31_timing_generator_create() local
1059 if (!tgn10) in dcn31_timing_generator_create()
1062 tgn10->base.inst = instance; in dcn31_timing_generator_create()
1063 tgn10->base.ctx = ctx; in dcn31_timing_generator_create()
1065 tgn10->tg_regs = &optc_regs[instance]; in dcn31_timing_generator_create()
1066 tgn10->tg_shift = &optc_shift; in dcn31_timing_generator_create()
1067 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
1069 dcn31_timing_generator_init(tgn10); in dcn31_timing_generator_create()
1071 return &tgn10->base; in dcn31_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| A D | dcn351_resource.c | 1012 struct optc *tgn10 = in dcn35_timing_generator_create() local
1015 if (!tgn10) in dcn35_timing_generator_create()
1025 tgn10->base.inst = instance; in dcn35_timing_generator_create()
1026 tgn10->base.ctx = ctx; in dcn35_timing_generator_create()
1028 tgn10->tg_regs = &optc_regs[instance]; in dcn35_timing_generator_create()
1029 tgn10->tg_shift = &optc_shift; in dcn35_timing_generator_create()
1030 tgn10->tg_mask = &optc_mask; in dcn35_timing_generator_create()
1032 dcn35_timing_generator_init(tgn10); in dcn35_timing_generator_create()
1034 return &tgn10->base; in dcn35_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| A D | dcn36_resource.c | 1013 struct optc *tgn10 = in dcn35_timing_generator_create() local
1016 if (!tgn10) in dcn35_timing_generator_create()
1026 tgn10->base.inst = instance; in dcn35_timing_generator_create()
1027 tgn10->base.ctx = ctx; in dcn35_timing_generator_create()
1029 tgn10->tg_regs = &optc_regs[instance]; in dcn35_timing_generator_create()
1030 tgn10->tg_shift = &optc_shift; in dcn35_timing_generator_create()
1031 tgn10->tg_mask = &optc_mask; in dcn35_timing_generator_create()
1033 dcn35_timing_generator_init(tgn10); in dcn35_timing_generator_create()
1035 return &tgn10->base; in dcn35_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| A D | dcn30_resource.c | 892 struct optc *tgn10 = in dcn30_timing_generator_create() local
895 if (!tgn10) in dcn30_timing_generator_create()
898 tgn10->base.inst = instance; in dcn30_timing_generator_create()
899 tgn10->base.ctx = ctx; in dcn30_timing_generator_create()
901 tgn10->tg_regs = &optc_regs[instance]; in dcn30_timing_generator_create()
902 tgn10->tg_shift = &optc_shift; in dcn30_timing_generator_create()
903 tgn10->tg_mask = &optc_mask; in dcn30_timing_generator_create()
905 dcn30_timing_generator_init(tgn10); in dcn30_timing_generator_create()
907 return &tgn10->base; in dcn30_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.c | 991 struct optc *tgn10 = in dcn401_timing_generator_create() local
994 if (!tgn10) in dcn401_timing_generator_create()
1003 tgn10->base.inst = instance; in dcn401_timing_generator_create()
1004 tgn10->base.ctx = ctx; in dcn401_timing_generator_create()
1006 tgn10->tg_regs = &optc_regs[instance]; in dcn401_timing_generator_create()
1007 tgn10->tg_shift = &optc_shift; in dcn401_timing_generator_create()
1008 tgn10->tg_mask = &optc_mask; in dcn401_timing_generator_create()
1010 dcn401_timing_generator_init(tgn10); in dcn401_timing_generator_create()
1012 return &tgn10->base; in dcn401_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| A D | dcn20_resource.c | 884 struct optc *tgn10 = in dcn20_timing_generator_create() local
887 if (!tgn10) in dcn20_timing_generator_create()
890 tgn10->base.inst = instance; in dcn20_timing_generator_create()
891 tgn10->base.ctx = ctx; in dcn20_timing_generator_create()
893 tgn10->tg_regs = &tg_regs[instance]; in dcn20_timing_generator_create()
894 tgn10->tg_shift = &tg_shift; in dcn20_timing_generator_create()
895 tgn10->tg_mask = &tg_mask; in dcn20_timing_generator_create()
897 dcn20_timing_generator_init(tgn10); in dcn20_timing_generator_create()
899 return &tgn10->base; in dcn20_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.c | 998 struct optc *tgn10 = in dcn32_timing_generator_create() local
1001 if (!tgn10) in dcn32_timing_generator_create()
1011 tgn10->base.inst = instance; in dcn32_timing_generator_create()
1012 tgn10->base.ctx = ctx; in dcn32_timing_generator_create()
1014 tgn10->tg_regs = &optc_regs[instance]; in dcn32_timing_generator_create()
1015 tgn10->tg_shift = &optc_shift; in dcn32_timing_generator_create()
1016 tgn10->tg_mask = &optc_mask; in dcn32_timing_generator_create()
1018 dcn32_timing_generator_init(tgn10); in dcn32_timing_generator_create()
1020 return &tgn10->base; in dcn32_timing_generator_create()
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