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Searched refs:threshold (Results 1 – 25 of 232) sorted by relevance

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/drivers/net/wireless/intel/ipw2x00/
A Dlibipw_spy.c118 struct iw_thrspy * threshold = (struct iw_thrspy *) extra; in ipw_wx_set_thrspy() local
125 spydata->spy_thr_low = threshold->low; in ipw_wx_set_thrspy()
126 spydata->spy_thr_high = threshold->high; in ipw_wx_set_thrspy()
152 threshold->low = spydata->spy_thr_low; in ipw_wx_get_thrspy()
153 threshold->high = spydata->spy_thr_high; in ipw_wx_get_thrspy()
169 struct iw_thrspy threshold; in iw_send_thrspy_event() local
175 memcpy(threshold.addr.sa_data, address, ETH_ALEN); in iw_send_thrspy_event()
176 threshold.addr.sa_family = ARPHRD_ETHER; in iw_send_thrspy_event()
178 threshold.qual = *wstats; in iw_send_thrspy_event()
180 threshold.low = spydata->spy_thr_low; in iw_send_thrspy_event()
[all …]
/drivers/soc/tegra/fuse/
A Dspeedo-tegra124.c51 int *threshold) in rev_sku_to_speedo_ids() argument
59 *threshold = THRESHOLD_INDEX_0; in rev_sku_to_speedo_ids()
77 *threshold = THRESHOLD_INDEX_0; in rev_sku_to_speedo_ids()
85 *threshold = THRESHOLD_INDEX_1; in rev_sku_to_speedo_ids()
93 *threshold = THRESHOLD_INDEX_1; in rev_sku_to_speedo_ids()
104 int i, threshold, soc_speedo_0_value; in tegra124_init_speedo_data() local
124 rev_sku_to_speedo_ids(sku_info, &threshold); in tegra124_init_speedo_data()
130 gpu_process_speedos[threshold][i]) in tegra124_init_speedo_data()
136 cpu_process_speedos[threshold][i]) in tegra124_init_speedo_data()
142 soc_process_speedos[threshold][i]) in tegra124_init_speedo_data()
A Dspeedo-tegra114.c34 int *threshold) in rev_sku_to_speedo_ids() argument
47 *threshold = THRESHOLD_INDEX_0; in rev_sku_to_speedo_ids()
54 *threshold = THRESHOLD_INDEX_1; in rev_sku_to_speedo_ids()
61 *threshold = THRESHOLD_INDEX_0; in rev_sku_to_speedo_ids()
77 int threshold; in tegra114_init_speedo_data() local
85 rev_sku_to_speedo_ids(sku_info, &threshold); in tegra114_init_speedo_data()
91 if (cpu_speedo_val < cpu_process_speedos[threshold][i]) in tegra114_init_speedo_data()
96 if (soc_speedo_val < soc_process_speedos[threshold][i]) in tegra114_init_speedo_data()
/drivers/cpuidle/governors/
A Dladder.c32 } threshold; member
90 last_residency > last_state->threshold.promotion_time_ns && in ladder_select_state()
94 if (last_state->stats.promotion_count >= last_state->threshold.promotion_count) { in ladder_select_state()
115 last_residency < last_state->threshold.demotion_time_ns) { in ladder_select_state()
118 if (last_state->stats.demotion_count >= last_state->threshold.demotion_count) { in ladder_select_state()
151 lstate->threshold.promotion_count = PROMOTION_COUNT; in ladder_enable_device()
152 lstate->threshold.demotion_count = DEMOTION_COUNT; in ladder_enable_device()
155 lstate->threshold.promotion_time_ns = state->exit_latency_ns; in ladder_enable_device()
157 lstate->threshold.demotion_time_ns = state->exit_latency_ns; in ladder_enable_device()
/drivers/gpu/drm/xe/
A Dxe_gt_sriov_pf_monitor.c44 static int pf_handle_vf_threshold_event(struct xe_gt *gt, u32 vfid, u32 threshold) in pf_handle_vf_threshold_event() argument
49 e = xe_guc_klv_threshold_key_to_index(threshold); in pf_handle_vf_threshold_event()
55 threshold, origin); in pf_handle_vf_threshold_event()
61 xe_guc_klv_key_to_string(threshold)); in pf_handle_vf_threshold_event()
82 u32 threshold; in xe_gt_sriov_pf_monitor_process_guc2pf() local
100 threshold = FIELD_GET(GUC2PF_ADVERSE_EVENT_EVENT_MSG_2_THRESHOLD, msg[2]); in xe_gt_sriov_pf_monitor_process_guc2pf()
105 return pf_handle_vf_threshold_event(gt, vfid, threshold); in xe_gt_sriov_pf_monitor_process_guc2pf()
/drivers/staging/axis-fifo/
A Daxis-fifo.txt38 - xlnx,rx-fifo-pe-threshold: RX programmable empty interrupt threshold
40 - xlnx,rx-fifo-pf-threshold: RX programmable full interrupt threshold
46 - xlnx,tx-fifo-pe-threshold: TX programmable empty interrupt threshold
48 - xlnx,tx-fifo-pf-threshold: TX programmable full interrupt threshold
80 xlnx,rx-fifo-pe-threshold = <0x2>;
81 xlnx,rx-fifo-pf-threshold = <0x1fb>;
86 xlnx,tx-fifo-pe-threshold = <0x200>;
87 xlnx,tx-fifo-pf-threshold = <0x7ffb>;
/drivers/gpu/host1x/hw/
A Dchannel_hw.c50 static void submit_wait(struct host1x_job *job, u32 id, u32 threshold, in submit_wait() argument
75 threshold, in submit_wait()
92 threshold, in submit_wait()
104 host1x_class_host_wait_syncpt(id, threshold) in submit_wait()
120 u32 threshold; in submit_gathers() local
127 threshold = job_syncpt_base + cmd->wait.threshold; in submit_gathers()
129 threshold = cmd->wait.threshold; in submit_gathers()
131 submit_wait(job, cmd->wait.id, threshold, cmd->wait.next_class); in submit_gathers()
A Dopcodes.h14 unsigned indx, unsigned threshold) in host1x_class_host_wait_syncpt() argument
17 | host1x_uclass_wait_syncpt_thresh_f(threshold); in host1x_class_host_wait_syncpt()
21 unsigned indx, unsigned threshold) in host1x_class_host_load_syncpt_base() argument
24 | host1x_uclass_load_syncpt_base_value_f(threshold); in host1x_class_host_load_syncpt_base()
/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_1.0/
A Dia_css_anr.host.c31 to->threshold = from->threshold; in ia_css_anr_encode()
42 "anr_threshold", anr->threshold); in ia_css_anr_dump()
52 config->threshold); in ia_css_anr_debug_dtrace()
/drivers/md/persistent-data/
A Ddm-space-map-metadata.c24 struct threshold { struct
27 dm_block_t threshold; argument
33 static void threshold_init(struct threshold *t) in threshold_init() argument
43 t->threshold = value; in set_threshold()
50 return t->threshold_set && value <= t->threshold; in below_threshold()
180 struct threshold threshold; member
504 check_threshold(&smm->threshold, count); in sm_metadata_new_block()
525 dm_block_t threshold, in sm_metadata_register_threshold_callback() argument
531 set_threshold(&smm->threshold, threshold, fn, context); in sm_metadata_register_threshold_callback()
796 threshold_init(&smm->threshold); in dm_sm_metadata_create()
[all …]
/drivers/iio/adc/
A Dxilinx-xadc-events.c168 *val = xadc->threshold[offset]; in xadc_read_event_value()
202 xadc->threshold[offset] = val; in xadc_write_event_value()
226 if (xadc->threshold[offset] < xadc->temp_hysteresis) in xadc_write_event_value()
227 xadc->threshold[offset + 4] = 0; in xadc_write_event_value()
229 xadc->threshold[offset + 4] = xadc->threshold[offset] - in xadc_write_event_value()
232 xadc->threshold[offset + 4]); in xadc_write_event_value()
/drivers/nvme/host/
A Dhwmon.c22 unsigned int threshold = sensor << NVME_TEMP_THRESH_SELECT_SHIFT; in nvme_get_temp_thresh() local
27 threshold |= NVME_TEMP_THRESH_TYPE_UNDER; in nvme_get_temp_thresh()
29 ret = nvme_get_features(ctrl, NVME_FEAT_TEMP_THRESH, threshold, NULL, 0, in nvme_get_temp_thresh()
43 unsigned int threshold = sensor << NVME_TEMP_THRESH_SELECT_SHIFT; in nvme_set_temp_thresh() local
47 threshold |= clamp_val(temp, 0, NVME_TEMP_THRESH_MASK); in nvme_set_temp_thresh()
50 threshold |= NVME_TEMP_THRESH_TYPE_UNDER; in nvme_set_temp_thresh()
52 ret = nvme_set_features(ctrl, NVME_FEAT_TEMP_THRESH, threshold, NULL, 0, in nvme_set_temp_thresh()
/drivers/iio/light/
A Dmax44009.c346 int reg, threshold; in max44009_write_event_value() local
351 threshold = max44009_threshold_byte_from_fraction(val, val2); in max44009_write_event_value()
352 if (threshold < 0) in max44009_write_event_value()
353 return threshold; in max44009_write_event_value()
359 return i2c_smbus_write_byte_data(data->client, reg, threshold); in max44009_write_event_value()
405 int threshold; in max44009_read_event_value() local
413 threshold = ret; in max44009_read_event_value()
415 *val = threshold * MAX44009_SCALE_NUMERATOR; in max44009_read_event_value()
/drivers/staging/media/atomisp/pci/isp/kernels/ynr/ynr_1.0/
A Dia_css_ynr.host.c37 to->threshold = in ia_css_nr_encode()
78 from->ee.threshold) >> 8; in ia_css_yee_encode()
81 from->ee.threshold) >> 8; in ia_css_yee_encode()
113 "ynr_threshold", ynr->threshold); in ia_css_nr_dump()
200 config->threshold, config->gain, config->detail_gain); in ia_css_ee_debug_dtrace()
/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_1.0/
A Dia_css_xnr.host.c37 to->threshold = in ia_css_xnr_encode()
38 (uint16_t)uDIGIT_FITTING(from->threshold, 16, SH_CSS_ISP_YUV_BITS); in ia_css_xnr_encode()
56 "config.threshold=%d\n", config->threshold); in ia_css_xnr_debug_dtrace()
/drivers/gpu/host1x/
A Dfence.c37 if (host1x_syncpt_is_expired(sf->sp, sf->threshold)) in host1x_syncpt_fence_enable_signaling()
125 struct dma_fence *host1x_fence_create(struct host1x_syncpt *sp, u32 threshold, in host1x_fence_create() argument
135 fence->threshold = threshold; in host1x_fence_create()
A Dintr.c20 if ((s32)(fence_in_list->threshold - fence->threshold) <= 0) { in host1x_intr_add_fence_to_list()
38 host1x_hw_intr_set_syncpt_threshold(host, sp->id, fence->threshold); in host1x_intr_update_hw_state()
86 if (((value - fence->threshold) & 0x80000000U) != 0U) { in host1x_intr_handle_interrupt()
/drivers/perf/arm_cspmu/
A Dampere_cspmu.c36 SOC_PMU_EVENT_ATTR_EXTRACTOR(threshold, config1, 0, 7);
105 ARM_CSPMU_FORMAT_ATTR(threshold, "config1:0-7"),
147 u32 threshold, rank, bank; in ampere_cspmu_set_ev_filter() local
149 threshold = get_threshold(event); in ampere_cspmu_set_ev_filter()
153 writel(threshold, cspmu->base0 + PMAUXR0); in ampere_cspmu_set_ev_filter()
/drivers/thermal/qcom/
A DKconfig10 Also able to set threshold temperature for both hot and cold and update
11 when a threshold is reached.
21 Thermal client sets threshold temperature for both warm and cool and
22 gets updated when a threshold is reached.
A Dqcom-spmi-temp-alarm.c315 u8 reg, threshold; in qpnp_tm_update_critical_trip_temp() local
327 threshold = THRESH_MIN; in qpnp_tm_update_critical_trip_temp()
332 threshold = THRESH_MAX - in qpnp_tm_update_critical_trip_temp()
337 threshold = THRESH_MAX; in qpnp_tm_update_critical_trip_temp()
348 memcpy(chip->temp_thresh_map, chip->data->temp_map[threshold], in qpnp_tm_update_critical_trip_temp()
350 reg |= threshold; in qpnp_tm_update_critical_trip_temp()
530 u8 reg, threshold; in qpnp_tm_sync_thresholds() local
537 threshold = reg & SHUTDOWN_CTRL1_THRESHOLD_MASK; in qpnp_tm_sync_thresholds()
538 memcpy(chip->temp_thresh_map, chip->data->temp_map[threshold], in qpnp_tm_sync_thresholds()
/drivers/thermal/
A Dgov_fair_share.c25 if (td->threshold > tz->temperature) in get_trip_level()
30 if (!level_td || td->threshold > level_td->threshold) in get_trip_level()
/drivers/dma/stm32/
A Dstm32-dma.c219 u32 threshold; member
284 u32 threshold) in stm32_dma_get_max_width() argument
288 if (threshold == STM32_DMA_FIFO_THRESHOLD_FULL) in stm32_dma_get_max_width()
308 if (threshold == STM32_DMA_FIFO_THRESHOLD_NONE) in stm32_dma_fifo_threshold_is_allowed()
318 (threshold + 1) / 4) % burst; in stm32_dma_fifo_threshold_is_allowed()
333 if (threshold == STM32_DMA_FIFO_THRESHOLD_NONE) in stm32_dma_is_burst_possible()
945 fifoth = chan->threshold; in stm32_dma_set_xfer_param()
1249 u32 num_sgs, best_burst, threshold; in stm32_dma_prep_dma_memcpy() local
1258 threshold = chan->threshold; in stm32_dma_prep_dma_memcpy()
1267 threshold, max_width); in stm32_dma_prep_dma_memcpy()
[all …]
/drivers/spi/
A Dspi-pxa2xx.c64 u32 threshold; member
277 u32 *sccr1_reg, u32 threshold) in pxa2xx_spi_set_rx_thre() argument
281 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); in pxa2xx_spi_set_rx_thre()
284 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold); in pxa2xx_spi_set_rx_thre()
287 *sccr1_reg |= SSCR1_RxTresh(threshold); in pxa2xx_spi_set_rx_thre()
580 threshold = chip->threshold; in reset_sccr1()
582 threshold = 0; in reset_sccr1()
597 pxa2xx_spi_update(drv_data, SSCR1, mask, threshold); in reset_sccr1()
1008 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; in pxa2xx_spi_transfer_one()
1213 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) in setup()
[all …]
/drivers/net/ethernet/samsung/sxgbe/
A Dsxgbe_mtl.c104 int threshold) in sxgbe_mtl_fc_active() argument
110 reg_val |= (threshold << RX_FC_ACTIVE); in sxgbe_mtl_fc_active()
125 int threshold) in sxgbe_mtl_fc_deactive() argument
131 reg_val |= (threshold << RX_FC_DEACTIVE); in sxgbe_mtl_fc_deactive()
/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_core_perf.c164 u32 bw, threshold; in dpu_core_perf_crtc_check() local
191 threshold = kms->perf.perf_cfg->max_bw_high; in dpu_core_perf_crtc_check()
193 DRM_DEBUG_ATOMIC("final threshold bw limit = %d\n", threshold); in dpu_core_perf_crtc_check()
195 if (!threshold) { in dpu_core_perf_crtc_check()
198 } else if (bw > threshold) { in dpu_core_perf_crtc_check()
200 threshold); in dpu_core_perf_crtc_check()

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