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Searched refs:tiling_flags (Results 1 – 25 of 29) sorted by relevance

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/drivers/gpu/drm/radeon/
A Dradeon_object.c529 lobj->tiling_flags = bo->tiling_flags; in radeon_bo_list_validate()
545 if (!bo->tiling_flags) in radeon_bo_get_surface_reg()
583 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, in radeon_bo_get_surface_reg()
605 uint32_t tiling_flags, uint32_t pitch) in radeon_bo_set_tiling_flags() argument
613 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_set_tiling_flags()
614 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; in radeon_bo_set_tiling_flags()
658 bo->tiling_flags = tiling_flags; in radeon_bo_set_tiling_flags()
665 uint32_t *tiling_flags, in radeon_bo_get_tiling_flags() argument
670 if (tiling_flags) in radeon_bo_get_tiling_flags()
671 *tiling_flags = bo->tiling_flags; in radeon_bo_get_tiling_flags()
[all …]
A Dradeon_fbdev.c64 u32 tiling_flags = 0; in radeon_fbdev_create_pinned_object() local
90 tiling_flags = RADEON_TILING_MACRO; in radeon_fbdev_create_pinned_object()
95 tiling_flags |= RADEON_TILING_SWAP_32BIT; in radeon_fbdev_create_pinned_object()
98 tiling_flags |= RADEON_TILING_SWAP_16BIT; in radeon_fbdev_create_pinned_object()
105 if (tiling_flags) { in radeon_fbdev_create_pinned_object()
107 tiling_flags | RADEON_TILING_SURFACE, in radeon_fbdev_create_pinned_object()
A Dr300.c719 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
721 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
723 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
788 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
790 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
792 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
873 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
875 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
877 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
A Dr200.c221 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
223 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
293 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
295 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
A Dradeon_object.h158 u32 tiling_flags, u32 pitch);
160 u32 *tiling_flags, u32 *pitch);
A Dradeon_legacy_crtc.c386 uint32_t tiling_flags; in radeon_crtc_do_set_base() local
464 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in radeon_crtc_do_set_base()
466 if (tiling_flags & RADEON_TILING_MICRO) in radeon_crtc_do_set_base()
483 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
499 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
A Devergreen_cs.c94 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags) in evergreen_cs_get_aray_mode() argument
96 if (tiling_flags & RADEON_TILING_MACRO) in evergreen_cs_get_aray_mode()
98 else if (tiling_flags & RADEON_TILING_MICRO) in evergreen_cs_get_aray_mode()
1183 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1186 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
1447 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1450 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
1475 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1478 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
2364 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_packet3_check()
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A Datombios_crtc.c1145 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in dce4_crtc_do_set_base() local
1182 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in dce4_crtc_do_set_base()
1265 if (tiling_flags & RADEON_TILING_MACRO) { in dce4_crtc_do_set_base()
1266 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base()
1339 } else if (tiling_flags & RADEON_TILING_MICRO) in dce4_crtc_do_set_base()
1466 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in avivo_crtc_do_set_base() local
1501 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in avivo_crtc_do_set_base()
1577 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base()
1579 else if (tiling_flags & RADEON_TILING_MICRO) in avivo_crtc_do_set_base()
1582 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base()
[all …]
A Dr100.c1312 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_reloc_pitch_offset()
1654 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1656 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
3112 uint32_t tiling_flags, uint32_t pitch, in r100_set_surface_reg() argument
3122 if (tiling_flags & RADEON_TILING_MACRO) in r100_set_surface_reg()
3129 if (tiling_flags & (RADEON_TILING_MACRO)) in r100_set_surface_reg()
3131 if (tiling_flags & RADEON_TILING_MICRO) in r100_set_surface_reg()
3134 if (tiling_flags & RADEON_TILING_MACRO) in r100_set_surface_reg()
3136 if (tiling_flags & RADEON_TILING_MICRO) in r100_set_surface_reg()
3140 if (tiling_flags & RADEON_TILING_SWAP_16BIT) in r100_set_surface_reg()
[all …]
A Dr600_cs.c1041 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1140 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1143 } else if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r600_cs_check_reg()
1474 u32 tiling_flags) in r600_check_texture_resource() argument
1496 if (tiling_flags & RADEON_TILING_MACRO) in r600_check_texture_resource()
1498 else if (tiling_flags & RADEON_TILING_MICRO) in r600_check_texture_resource()
1967 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r600_packet3_check()
1969 else if (reloc->tiling_flags & RADEON_TILING_MICRO) in r600_packet3_check()
1985 reloc->tiling_flags); in r600_packet3_check()
A Dradeon_gem.c568 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); in radeon_gem_set_tiling_ioctl()
589 radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); in radeon_gem_get_tiling_ioctl()
A Dradeon_vm.c146 list[0].tiling_flags = 0; in radeon_vm_get_bos()
157 list[idx].tiling_flags = 0; in radeon_vm_get_bos()
A Dradeon_display.c491 uint32_t tiling_flags, pitch_pixels; in radeon_crtc_page_flip_target() local
543 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); in radeon_crtc_page_flip_target()
551 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_page_flip_target()
A Dradeon.h355 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
462 uint32_t tiling_flags; member
493 u32 tiling_flags; member
1925 uint32_t tiling_flags, uint32_t pitch,
/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_display.c204 u64 tiling_flags; in amdgpu_display_crtc_page_flip_target() local
260 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); in amdgpu_display_crtc_page_flip_target()
736 AMDGPU_TILING_GET(afb->tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK); in convert_tiling_flags_to_modifier_gfx12()
761 if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) { in convert_tiling_flags_to_modifier()
764 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE); in convert_tiling_flags_to_modifier()
891 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1; in convert_tiling_flags_to_modifier()
953 micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE); in check_tiling_flags_gfx6()
1164 uint64_t *tiling_flags, bool *tmz_surface, in amdgpu_display_get_fb_info() argument
1171 *tiling_flags = 0; in amdgpu_display_get_fb_info()
1187 amdgpu_bo_get_tiling_flags(rbo, tiling_flags); in amdgpu_display_get_fb_info()
[all …]
A Damdgpu_object.h130 u64 tiling_flags; member
288 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
289 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
A Damdgpu_object.c1115 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) in amdgpu_bo_set_tiling_flags() argument
1122 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) in amdgpu_bo_set_tiling_flags()
1126 ubo->tiling_flags = tiling_flags; in amdgpu_bo_set_tiling_flags()
1138 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) in amdgpu_bo_get_tiling_flags() argument
1146 if (tiling_flags) in amdgpu_bo_get_tiling_flags()
1147 *tiling_flags = ubo->tiling_flags; in amdgpu_bo_get_tiling_flags()
A Ddce_v8_0.c1802 uint64_t fb_location, tiling_flags; in dce_v8_0_crtc_do_set_base() local
1840 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v8_0_crtc_do_set_base()
1843 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v8_0_crtc_do_set_base()
1925 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
1928 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v8_0_crtc_do_set_base()
1929 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v8_0_crtc_do_set_base()
1930 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v8_0_crtc_do_set_base()
1931 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v8_0_crtc_do_set_base()
1932 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v8_0_crtc_do_set_base()
1941 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
A Ddce_v6_0.c1893 uint64_t fb_location, tiling_flags; in dce_v6_0_crtc_do_set_base() local
1930 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v6_0_crtc_do_set_base()
2013 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
2016 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v6_0_crtc_do_set_base()
2017 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v6_0_crtc_do_set_base()
2018 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v6_0_crtc_do_set_base()
2019 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v6_0_crtc_do_set_base()
2020 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v6_0_crtc_do_set_base()
2028 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
2032 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v6_0_crtc_do_set_base()
A Ddce_v10_0.c1855 uint64_t fb_location, tiling_flags; in dce_v10_0_crtc_do_set_base() local
1893 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v10_0_crtc_do_set_base()
1896 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v10_0_crtc_do_set_base()
1986 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
1989 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v10_0_crtc_do_set_base()
1990 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v10_0_crtc_do_set_base()
1991 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v10_0_crtc_do_set_base()
1992 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v10_0_crtc_do_set_base()
1993 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v10_0_crtc_do_set_base()
2006 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
A Damdgpu_ttm.c312 uint64_t from, to, cur_size, tiling_flags; in amdgpu_ttm_copy_mem_to_mem() local
340 amdgpu_bo_get_tiling_flags(abo_dst, &tiling_flags); in amdgpu_ttm_copy_mem_to_mem()
341 max_com = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK); in amdgpu_ttm_copy_mem_to_mem()
342 num_type = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_NUMBER_TYPE); in amdgpu_ttm_copy_mem_to_mem()
343 data_format = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_DATA_FORMAT); in amdgpu_ttm_copy_mem_to_mem()
345 AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_WRITE_COMPRESS_DISABLE); in amdgpu_ttm_copy_mem_to_mem()
A Ddce_v11_0.c1905 uint64_t fb_location, tiling_flags; in dce_v11_0_crtc_do_set_base() local
1943 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v11_0_crtc_do_set_base()
1946 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v11_0_crtc_do_set_base()
2036 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
2039 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v11_0_crtc_do_set_base()
2040 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v11_0_crtc_do_set_base()
2041 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v11_0_crtc_do_set_base()
2042 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v11_0_crtc_do_set_base()
2043 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v11_0_crtc_do_set_base()
2056 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
A Damdgpu_mode.h302 uint64_t tiling_flags; member
/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_plane.c181 uint64_t tiling_flags) in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags() argument
184 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
187 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
188 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
189 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
190 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
191 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
204 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
210 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
842 const uint64_t tiling_flags, in amdgpu_dm_plane_fill_plane_buffer_attributes() argument
[all …]
A Damdgpu_dm_plane.h49 const uint64_t tiling_flags,

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