| /drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_debug.c | 110 update->plane_info->tiling_info.gfx8.num_banks, in update_surface_trace()
111 update->plane_info->tiling_info.gfx8.bank_width, in update_surface_trace()
112 update->plane_info->tiling_info.gfx8.bank_width_c, in update_surface_trace()
113 update->plane_info->tiling_info.gfx8.bank_height, in update_surface_trace()
115 update->plane_info->tiling_info.gfx8.tile_aspect, in update_surface_trace()
117 update->plane_info->tiling_info.gfx8.tile_split, in update_surface_trace()
118 update->plane_info->tiling_info.gfx8.tile_split_c, in update_surface_trace()
119 update->plane_info->tiling_info.gfx8.tile_mode, in update_surface_trace()
127 update->plane_info->tiling_info.gfx8.pipe_config, in update_surface_trace()
128 update->plane_info->tiling_info.gfx8.array_mode, in update_surface_trace()
[all …]
|
| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| A D | amdgpu_dm_plane.c | 196 tiling_info->gfx8.array_mode = in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
202 tiling_info->gfx8.tile_mode = in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
209 tiling_info->gfx8.pipe_config = in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
217 tiling_info->gfx9.num_pipes = in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
219 tiling_info->gfx9.num_banks = in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
221 tiling_info->gfx9.pipe_interleave = in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
227 tiling_info->gfx9.num_rb_per_se = in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
229 tiling_info->gfx9.shaderEnable = 1; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
852 memset(tiling_info, 0, sizeof(*tiling_info)); in amdgpu_dm_plane_fill_plane_buffer_attributes()
906 tiling_info, dcc, in amdgpu_dm_plane_fill_plane_buffer_attributes()
[all …]
|
| A D | amdgpu_dm_plane.h | 50 struct dc_tiling_info *tiling_info,
|
| /drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_mem_input.c | 101 struct dc_tiling_info *tiling_info) in get_mi_tiling() argument
103 switch (tiling_info->gfx8.array_mode) { in get_mi_tiling()
136 struct dc_tiling_info *tiling_info, in dce_mi_program_pte_vm() argument
141 enum mi_tiling_format mi_tiling = get_mi_tiling(tiling_info); in dce_mi_program_pte_vm()
653 struct dc_tiling_info *tiling_info, in dce_mi_program_surface_config() argument
662 program_tiling(dce_mi, tiling_info); in dce_mi_program_surface_config()
673 struct dc_tiling_info *tiling_info, in dce60_mi_program_surface_config() argument
682 program_tiling(dce_mi, tiling_info); in dce60_mi_program_surface_config()
|
| /drivers/gpu/drm/amd/display/dc/dce110/ |
| A D | dce110_mem_input_v.c | 526 struct dc_tiling_info *tiling_info, in get_dvmm_hw_setting() argument
544 switch (tiling_info->gfx8.array_mode) { in get_dvmm_hw_setting()
566 struct dc_tiling_info *tiling_info, in dce_mem_input_v_program_pte_vm() argument
570 const unsigned int *pte = get_dvmm_hw_setting(tiling_info, format, false); in dce_mem_input_v_program_pte_vm()
571 const unsigned int *pte_chroma = get_dvmm_hw_setting(tiling_info, format, true); in dce_mem_input_v_program_pte_vm()
639 struct dc_tiling_info *tiling_info, in dce_mem_input_v_program_surface_config() argument
648 program_tiling(mem_input110, tiling_info, format); in dce_mem_input_v_program_surface_config()
|
| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | mem_input.h | 153 struct dc_tiling_info *tiling_info,
167 struct dc_tiling_info *tiling_info,
|
| A D | hubp.h | 181 struct dc_tiling_info *tiling_info,
195 struct dc_tiling_info *tiling_info,
|
| /drivers/gpu/drm/amd/display/dc/hubp/dcn201/ |
| A D | dcn201_hubp.c | 45 struct dc_tiling_info *tiling_info, in hubp201_program_surface_config() argument
53 hubp1_program_tiling(hubp, tiling_info, format); in hubp201_program_surface_config()
|
| /drivers/gpu/drm/amd/display/dc/hubp/dcn35/ |
| A D | dcn35_hubp.c | 175 struct dc_tiling_info *tiling_info, in hubp35_program_surface_config() argument
185 hubp3_program_tiling(hubp2, tiling_info, format); in hubp35_program_surface_config()
|
| A D | dcn35_hubp.h | 68 struct dc_tiling_info *tiling_info,
|
| /drivers/gpu/drm/amd/display/dc/hwss/dce60/ |
| A D | dce60_hwseq.c | 105 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) in dce60_should_enable_fbc()
319 &plane_state->tiling_info, in dce60_program_front_end_for_pipe()
331 &plane_state->tiling_info, in dce60_program_front_end_for_pipe()
|
| /drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| A D | dml21_utils.c | 303 memcpy(&phantom_plane->tiling_info, &main_plane->tiling_info, in dml21_add_phantom_plane()
304 sizeof(phantom_plane->tiling_info)); in dml21_add_phantom_plane()
|
| A D | dml21_translation_helper.c | 799 switch (plane_state->tiling_info.gfxversion) { in populate_dml21_surface_config_from_plane_state()
806 surface->tiling = gfx9_to_dml2_swizzle_mode(plane_state->tiling_info.gfx9.swizzle); in populate_dml21_surface_config_from_plane_state()
809 surface->tiling = gfx_addr3_to_dml2_swizzle_mode(plane_state->tiling_info.gfx_addr3.swizzle); in populate_dml21_surface_config_from_plane_state()
|
| /drivers/gpu/drm/amd/display/dc/hubp/dcn30/ |
| A D | dcn30_hubp.c | 414 struct dc_tiling_info *tiling_info, in hubp3_program_surface_config() argument
424 hubp3_program_tiling(hubp2, tiling_info, format); in hubp3_program_surface_config()
|
| A D | dcn30_hubp.h | 267 struct dc_tiling_info *tiling_info,
|
| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | dml2_mall_phantom.c | 765 memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info, in enable_phantom_plane()
766 sizeof(phantom_plane->tiling_info)); in enable_phantom_plane()
|
| /drivers/gpu/drm/amd/display/dc/hubp/dcn401/ |
| A D | dcn401_hubp.c | 595 struct dc_tiling_info *tiling_info, in hubp401_program_surface_config() argument
605 hubp401_program_tiling(hubp2, tiling_info, format); in hubp401_program_surface_config()
|
| A D | dcn401_hubp.h | 291 struct dc_tiling_info *tiling_info,
|
| /drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_gem.c | 723 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); in amdgpu_gem_metadata_ioctl()
733 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); in amdgpu_gem_metadata_ioctl()
|
| /drivers/gpu/drm/amd/display/dc/hubp/dcn20/ |
| A D | dcn20_hubp.h | 384 struct dc_tiling_info *tiling_info,
|
| /drivers/gpu/drm/amd/display/dc/hubp/dcn10/ |
| A D | dcn10_hubp.c | 558 struct dc_tiling_info *tiling_info, in hubp1_program_surface_config() argument
566 hubp1_program_tiling(hubp, tiling_info, format); in hubp1_program_surface_config()
|
| /drivers/gpu/drm/amd/display/dc/ |
| A D | dc.h | 1384 struct dc_tiling_info tiling_info; member
1457 struct dc_tiling_info tiling_info; member
|
| /drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| A D | dcn_calcs.c | 339 input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle; in pipe_ctx_to_e2e_pipe_params()
348 …input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.s… in pipe_ctx_to_e2e_pipe_params()
1010 pipe->plane_state->tiling_info.gfx9.swizzle); in dcn_validate_bandwidth()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource_helpers.c | 404 …if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfx9.swiz… in dcn32_set_det_allocations()
|
| A D | dcn32_resource.c | 1665 memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info, in dcn32_enable_phantom_plane()
1666 sizeof(phantom_plane->tiling_info)); in dcn32_enable_phantom_plane()
|