Searched refs:tiling_mode (Results 1 – 6 of 6) sorted by relevance
| /drivers/gpu/drm/i915/gem/ |
| A D | i915_gem_tiling.c | 161 int tiling_mode, unsigned int stride) in i915_vma_fence_prepare() argument
183 int tiling_mode, unsigned int stride) in i915_gem_object_fence_prepare() argument
191 if (tiling_mode == I915_TILING_NONE) in i915_gem_object_fence_prepare()
200 if (i915_vma_fence_prepare(vma, tiling_mode, stride)) in i915_gem_object_fence_prepare()
366 if (!i915_tiling_ok(obj, args->tiling_mode, args->stride)) { in i915_gem_set_tiling_ioctl()
371 if (args->tiling_mode == I915_TILING_NONE) { in i915_gem_set_tiling_ioctl()
375 if (args->tiling_mode == I915_TILING_X) in i915_gem_set_tiling_ioctl()
394 args->tiling_mode = I915_TILING_NONE; in i915_gem_set_tiling_ioctl()
404 args->tiling_mode = i915_gem_object_get_tiling(obj); in i915_gem_set_tiling_ioctl()
439 args->tiling_mode = in i915_gem_get_tiling_ioctl()
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| /drivers/gpu/drm/i915/gvt/ |
| A D | dmabuf.c | 217 unsigned int tiling_mode = 0; in vgpu_create_gem() local
222 tiling_mode = I915_TILING_NONE; in vgpu_create_gem()
225 tiling_mode = I915_TILING_X; in vgpu_create_gem()
230 tiling_mode = I915_TILING_Y; in vgpu_create_gem()
237 obj->tiling_and_stride = tiling_mode | stride; in vgpu_create_gem()
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| /drivers/gpu/drm/amd/display/dc/basics/ |
| A D | dce_calcs.c | 107 enum bw_defines *tiling_mode; in calculate_bandwidth() local
131 tiling_mode = kcalloc(maximum_number_of_surfaces, sizeof(*tiling_mode), GFP_KERNEL); in calculate_bandwidth()
132 if (!tiling_mode) in calculate_bandwidth()
274 tiling_mode[0] = bw_def_linear; in calculate_bandwidth()
275 tiling_mode[1] = bw_def_linear; in calculate_bandwidth()
276 tiling_mode[2] = bw_def_linear; in calculate_bandwidth()
277 tiling_mode[3] = bw_def_linear; in calculate_bandwidth()
280 tiling_mode[0] = bw_def_landscape; in calculate_bandwidth()
339 tiling_mode[i] = bw_def_linear; in calculate_bandwidth()
342 tiling_mode[i] = bw_def_tiled; in calculate_bandwidth()
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| /drivers/gpu/drm/amd/display/dc/ |
| A D | dc_types.h | 81 enum tiling_mode { enum
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| A D | dml2_core_shared_types.h | 2032 unsigned int tiling_mode; member
2101 unsigned int tiling_mode; member
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| A D | dml2_core_dcn4_calcs.c | 2279 DML_LOG_VERBOSE("DML::%s: tiling_mode = %u\n", __func__, p->tiling_mode); in calculate_mcache_row_bytes()
2301 blk_bytes = dml_get_tile_block_size_bytes(p->tiling_mode); in calculate_mcache_row_bytes()
2444 l->l_p.tiling_mode = p->tiling_mode; in calculate_mcache_setting()
2480 l->c_p.tiling_mode = p->tiling_mode; in calculate_mcache_setting()
9319 calculate_mcache_setting_params->tiling_mode = display_cfg->plane_descriptors[k].surface.tiling; in dml_core_mode_support()
10791 calculate_mcache_setting_params->tiling_mode = display_cfg->plane_descriptors[k].surface.tiling; in dml_core_mode_programming()
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