| /drivers/gpu/drm/i915/gt/ |
| A D | intel_tlb.c | 137 mutex_lock(>->tlb.invalidate_lock); in intel_gt_invalidate_tlb_full()
154 write_seqcount_invalidate(>->tlb.seqno); in intel_gt_invalidate_tlb_full()
156 mutex_unlock(>->tlb.invalidate_lock); in intel_gt_invalidate_tlb_full()
162 mutex_init(>->tlb.invalidate_lock); in intel_gt_init_tlb()
163 seqcount_mutex_init(>->tlb.seqno, >->tlb.invalidate_lock); in intel_gt_init_tlb()
168 mutex_destroy(>->tlb.invalidate_lock); in intel_gt_fini_tlb()
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| A D | intel_tlb.h | 21 return seqprop_sequence(>->tlb.seqno); in intel_gt_tlb_seqno()
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| A D | intel_gt_types.h | 124 } tlb; member
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| A D | intel_ppgtt.c | 214 vma_invalidate_tlb(vm, vma_res->tlb); in ppgtt_unbind_vma()
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| /drivers/gpu/drm/msm/ |
| A D | msm_iommu.c | 29 const struct iommu_flush_ops *tlb; member
449 pagetable->tlb->tlb_flush_all((void *)adreno_smmu->cookie); in msm_iommu_tlb_flush_all()
465 pagetable->tlb->tlb_flush_walk(iova, size, granule, (void *)adreno_smmu->cookie); in msm_iommu_tlb_flush_walk()
527 ttbr0_cfg.tlb = &tlb_ops; in msm_iommu_pagetable_create()
601 pagetable->tlb = ttbr1_cfg->tlb; in msm_iommu_pagetable_create()
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| /drivers/gpu/drm/i915/ |
| A D | i915_vma_resource.c | 231 u32 *tlb) in i915_vma_resource_unbind() argument
235 vma_res->tlb = tlb; in i915_vma_resource_unbind()
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| A D | i915_vma_resource.h | 138 u32 *tlb; member
152 u32 *tlb);
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| A D | i915_vma.c | 1373 void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb) in vma_invalidate_tlb() argument
1378 if (!tlb) in vma_invalidate_tlb()
1390 WRITE_ONCE(tlb[id], in vma_invalidate_tlb()
2081 vma->obj->mm.tlb); in __i915_vma_evict()
2098 vma_invalidate_tlb(vma->vm, vma->obj->mm.tlb); in __i915_vma_evict()
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| A D | i915_vma.h | 263 void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb);
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| /drivers/gpu/drm/imagination/ |
| A D | pvr_rogue_mips_check.h | 51 static_assert(offsetof(struct rogue_mips_state, tlb) == 44,
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| A D | pvr_rogue_mips.h | 329 struct rogue_mips_tlb_entry tlb[ROGUE_MIPSFW_NUMBER_OF_TLB_ENTRIES]; member
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| /drivers/gpu/drm/i915/gem/ |
| A D | i915_gem_pages.c | 203 if (!obj->mm.tlb[id]) in flush_tlb_invalidate()
206 intel_gt_invalidate_tlb_full(gt, obj->mm.tlb[id]); in flush_tlb_invalidate()
207 obj->mm.tlb[id] = 0; in flush_tlb_invalidate()
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| A D | i915_gem_object_types.h | 691 u32 tlb[I915_MAX_GT]; member
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| /drivers/thermal/tegra/ |
| A D | soctherm.c | 1535 u32 *tlb; in soctherm_thermtrips_parse() local
1550 tlb = devm_kcalloc(&pdev->dev, max_num_prop, sizeof(u32), GFP_KERNEL); in soctherm_thermtrips_parse()
1551 if (!tlb) in soctherm_thermtrips_parse()
1554 tlb, n); in soctherm_thermtrips_parse()
1562 if (tlb[j] >= TEGRA124_SOCTHERM_SENSOR_NUM) in soctherm_thermtrips_parse()
1565 tt[i].id = tlb[j]; in soctherm_thermtrips_parse()
1566 tt[i].temp = tlb[j + 1]; in soctherm_thermtrips_parse()
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| /drivers/iommu/ |
| A D | omap-iommu-debug.c | 239 DEFINE_SHOW_ATTRIBUTE(tlb);
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| A D | msm_iommu.c | 347 .tlb = &msm_iommu_flush_ops, in msm_iommu_domain_config()
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| A D | io-pgtable-arm-v7s.c | 815 .tlb = &dummy_tlb_ops, in arm_v7s_do_selftests()
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| A D | ipmmu-vmsa.c | 436 domain->cfg.tlb = &ipmmu_flush_ops; in ipmmu_domain_init_context()
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| A D | io-pgtable-arm.c | 1436 .tlb = &dummy_tlb_ops, in arm_lpae_do_selftests()
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| /drivers/iommu/arm/arm-smmu/ |
| A D | qcom_iommu.c | 235 .tlb = &qcom_flush_ops, in qcom_iommu_init_domain()
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| A D | arm-smmu.c | 812 .tlb = smmu_domain->flush_ops, in arm_smmu_init_domain_context()
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| /drivers/gpu/drm/panfrost/ |
| A D | panfrost_mmu.c | 757 .tlb = &mmu_tlb_ops, in panfrost_mmu_ctx_create()
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| /drivers/gpu/drm/panthor/ |
| A D | panthor_mmu.c | 2347 .tlb = &mmu_tlb_ops, in panthor_vm_create()
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| /drivers/iommu/arm/arm-smmu-v3/ |
| A D | arm-smmu-v3.c | 2544 .tlb = &arm_smmu_flush_ops, in arm_smmu_domain_finalise()
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