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Searched refs:train (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/tegra/
A Ddp.c390 train->clock_recovered = false; in drm_dp_link_train_init()
391 train->channel_equalized = false; in drm_dp_link_train_init()
396 return train->clock_recovered && train->channel_equalized; in drm_dp_link_train_valid()
447 pattern |= link->train.pattern; in drm_dp_link_apply_training()
462 switch (link->train.pattern) { in drm_dp_link_train_wait()
548 link->train.clock_recovered = true; in drm_dp_link_recover_clock()
568 if (link->train.clock_recovered) in drm_dp_link_clock_recovery()
597 link->train.clock_recovered = false; in drm_dp_link_equalize_channel()
627 if (link->train.channel_equalized) in drm_dp_link_channel_equalization()
686 if (!link->train.clock_recovered) { in drm_dp_link_train_full()
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A Ddp.h159 struct drm_dp_link_train train; member
172 void drm_dp_link_train_init(struct drm_dp_link_train *train);
A Dsor.c813 u8 vs = link->train.request.voltage_swing[i]; in tegra_sor_dp_link_apply_training()
814 u8 pe = link->train.request.pre_emphasis[i]; in tegra_sor_dp_link_apply_training()
815 u8 pc = link->train.request.post_cursor[i]; in tegra_sor_dp_link_apply_training()
825 switch (link->train.pattern) { in tegra_sor_dp_link_apply_training()
/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
A Dramgt215.c138 train->r_100720 = 0; in gt215_link_train_calc()
147 train->r_111400 = 0x0; in gt215_link_train_calc()
178 train->state = NVA3_TRAIN_EXEC; in gt215_link_train()
223 ram_wr32(fuc, 0x100720, train->r_100720); in gt215_link_train()
249 gt215_link_train_calc(result, train); in gt215_link_train()
252 train->r_1111e0, train->r_111400); in gt215_link_train()
256 train->state = NVA3_TRAIN_DONE; in gt215_link_train()
264 train->state = NVA3_TRAIN_UNSUPPORTED; in gt215_link_train()
289 train->state = NVA3_TRAIN_UNSUPPORTED; in gt215_link_train_init()
299 train->state = NVA3_TRAIN_ONCE; in gt215_link_train_init()
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A Dramgk104.c1272 struct gk104_ram_train *train) in gk104_ram_train_type() argument
1288 case 0x00: value = &train->type00; break; in gk104_ram_train_type()
1327 train->mask |= 1 << M0205E.type; in gk104_ram_train_type()
1338 if ((train->mask & 0x03d3) != 0x03d3) { in gk104_ram_train_init_0()
1347 train->type08.data[i] << 4 | in gk104_ram_train_init_0()
1348 train->type06.data[i]); in gk104_ram_train_init_0()
1351 train->type09.data[i] << 4 | in gk104_ram_train_init_0()
1352 train->type07.data[i]); in gk104_ram_train_init_0()
1371 struct gk104_ram_train *train; in gk104_ram_train_init() local
1374 if (!(train = kzalloc(sizeof(*train), GFP_KERNEL))) in gk104_ram_train_init()
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/drivers/gpu/drm/nouveau/nvkm/engine/disp/
A Doutp.h112 int (*train)(struct nvkm_outp *, bool retrain); member
A Duoutp.c114 if (!outp->func->dp.train) in nvkm_uoutp_mthd_dp_train()
126 return outp->func->dp.train(outp, args->v0.retrain); in nvkm_uoutp_mthd_dp_train()
A Ddp.c629 .dp.train = nvkm_dp_train,
/drivers/gpu/drm/xlnx/
A Dzynqmp_dp.c739 u8 train = train_set[i]; in zynqmp_dp_update_vs_emph() local
741 opts.dp.voltage[0] = (train & DP_TRAIN_VOLTAGE_SWING_MASK) in zynqmp_dp_update_vs_emph()
743 opts.dp.pre[0] = (train & DP_TRAIN_PRE_EMPHASIS_MASK) in zynqmp_dp_update_vs_emph()
/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/
A Ddisp.c1166 .dp.train = r535_dp_train,

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