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Searched refs:ttbr (Results 1 – 19 of 19) sorted by relevance

/drivers/gpu/drm/msm/
A Dmsm_iommu.c32 phys_addr_t ttbr; member
245 phys_addr_t *ttbr, int *asid) in msm_iommu_pagetable_params() argument
254 if (ttbr) in msm_iommu_pagetable_params()
255 *ttbr = pagetable->ttbr; in msm_iommu_pagetable_params()
603 pagetable->ttbr = ttbr0_cfg.arm_lpae_s1_cfg.ttbr; in msm_iommu_pagetable_create()
A Dmsm_mmu.h90 int msm_iommu_pagetable_params(struct msm_mmu *mmu, phys_addr_t *ttbr,
/drivers/iommu/arm/arm-smmu/
A Darm-smmu.c547 cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr; in arm_smmu_init_context_bank()
548 cb->ttbr[1] = 0; in arm_smmu_init_context_bank()
550 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, in arm_smmu_init_context_bank()
552 cb->ttbr[1] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, in arm_smmu_init_context_bank()
556 cb->ttbr[1] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in arm_smmu_init_context_bank()
558 cb->ttbr[0] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in arm_smmu_init_context_bank()
561 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; in arm_smmu_init_context_bank()
636 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
637 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR1, cb->ttbr[1]); in arm_smmu_write_context_bank()
639 arm_smmu_cb_writeq(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
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A Darm-smmu-qcom.c247 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); in qcom_adreno_smmu_set_ttbr0_cfg()
259 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in qcom_adreno_smmu_set_ttbr0_cfg()
260 cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); in qcom_adreno_smmu_set_ttbr0_cfg()
A Darm-smmu.h366 u64 ttbr[2]; member
A Dqcom_iommu.c279 pgtbl_cfg.arm_lpae_s1_cfg.ttbr | in qcom_iommu_init_domain()
/drivers/iommu/
A Dapple-dart.c147 #define DART_TTBR(dart, sid, idx) ((dart)->hw->ttbr + \
181 u64 ttbr; member
568 pgtbl_cfg->apple_dart_cfg.ttbr[i]); in apple_dart_setup_translation()
1219 .ttbr = DART_T8020_TTBR,
1245 .ttbr = DART_T8020_USB4_TTBR,
1271 .ttbr = DART_T8020_TTBR,
1296 .ttbr = DART_T8110_TTBR,
A Dipmmu-vmsa.c366 u64 ttbr; in ipmmu_domain_setup_context() local
370 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr; in ipmmu_domain_setup_context()
371 ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr); in ipmmu_domain_setup_context()
372 ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32); in ipmmu_domain_setup_context()
A Dio-pgtable-arm-v7s.c755 cfg->arm_v7s_cfg.ttbr = paddr | upper_32_bits(paddr); in arm_v7s_alloc_pgtable()
757 cfg->arm_v7s_cfg.ttbr = paddr | ARM_V7S_TTBR_S | in arm_v7s_alloc_pgtable()
A Dio-pgtable-dart.c412 cfg->apple_dart_cfg.ttbr[i] = virt_to_phys(data->pgd[i]); in apple_dart_alloc_pgtable()
A Dmtk_iommu.c754 writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_attach_device()
1494 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_runtime_resume()
A Dmsm_iommu.c274 SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr); in __program_context()
A Dio-pgtable-arm.c1058 cfg->arm_lpae_s1_cfg.ttbr = virt_to_phys(data->pgd); in arm_64_lpae_alloc_pgtable_s1()
/drivers/gpu/drm/msm/adreno/
A Da6xx_preempt.c340 phys_addr_t ttbr; in preempt_init_ring() local
380 msm_iommu_pagetable_params(to_msm_vm(gpu->vm)->mmu, &ttbr, &asid); in preempt_init_ring()
383 smmu_info_ptr->ttbr0 = ttbr; in preempt_init_ring()
A Da6xx_gpu.c117 phys_addr_t ttbr; in a6xx_set_pagetable() local
124 if (msm_iommu_pagetable_params(to_msm_vm(vm)->mmu, &ttbr, &asid)) in a6xx_set_pagetable()
163 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr))); in a6xx_set_pagetable()
166 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) | in a6xx_set_pagetable()
178 OUT_RING(ring, lower_32_bits(ttbr)); in a6xx_set_pagetable()
179 OUT_RING(ring, upper_32_bits(ttbr)); in a6xx_set_pagetable()
/drivers/gpu/drm/panfrost/
A Dpanfrost_mmu.c225 if (drm_WARN_ON(pfdev->ddev, pgtbl_cfg->arm_lpae_s1_cfg.ttbr & in mmu_cfg_init_aarch64_4k()
229 mmu->cfg.transtab = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in mmu_cfg_init_aarch64_4k()
/drivers/iommu/arm/arm-smmu-v3/
A Darm-smmu-v3-test.c465 io_pgtable.cfg.arm_lpae_s1_cfg.ttbr = 0xdaedbeefdeadbeefULL; in arm_smmu_test_make_s1_cd()
A Darm-smmu-v3.c1411 target->data[1] = cpu_to_le64(pgtbl_cfg->arm_lpae_s1_cfg.ttbr & in arm_smmu_make_s1_cd()
/drivers/gpu/drm/panthor/
A Dpanthor_mmu.c756 transtab = cfg->arm_lpae_s1_cfg.ttbr; in panthor_vm_active()

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