| /drivers/net/ethernet/stmicro/stmmac/ |
| A D | dwmac-mediatek.c | 70 u32 tx_delay; member 150 mac_delay->tx_delay /= 550; in mt2712_delay_ps2stage() 158 mac_delay->tx_delay /= 170; in mt2712_delay_ps2stage() 175 mac_delay->tx_delay *= 550; in mt2712_delay_stage2ps() 183 mac_delay->tx_delay *= 170; in mt2712_delay_stage2ps() 202 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->tx_delay); in mt2712_set_delay() 330 mac_delay->tx_delay /= 290; in mt8195_delay_ps2stage() 339 mac_delay->tx_delay *= 290; in mt8195_delay_stage2ps() 368 !!mac_delay->tx_delay); in mt8195_set_delay() 370 mac_delay->tx_delay); in mt8195_set_delay() [all …]
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| A D | dwmac-rk.c | 38 int tx_delay, int rx_delay); 87 int tx_delay; member 309 int tx_delay, int rx_delay) in rk3128_set_to_rgmii() argument 381 int tx_delay, int rx_delay) in rk3228_set_to_rgmii() argument 463 int tx_delay, int rx_delay) in rk3288_set_to_rgmii() argument 568 int tx_delay, int rx_delay) in rk3328_set_to_rgmii() argument 660 int tx_delay, int rx_delay) in rk3366_set_to_rgmii() argument 727 int tx_delay, int rx_delay) in rk3368_set_to_rgmii() argument 1541 bsp_priv->tx_delay = 0x30; in rk_gmac_setup() 1544 bsp_priv->tx_delay); in rk_gmac_setup() [all …]
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| A D | dwmac-ingenic.c | 64 int tx_delay; member 208 if (mac->tx_delay == 0) in x2000_mac_set_mode() 212 FIELD_PREP(MACPHYC_TX_DELAY_MASK, (mac->tx_delay + 9750) / 19500 - 1); in x2000_mac_set_mode() 269 mac->tx_delay = tx_delay_ps * 1000; in ingenic_mac_probe()
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| /drivers/net/hamradio/ |
| A D | hdlcdrv.c | 226 s->ch_params.tx_delay = data[1]; in do_kiss_params() 227 PKP("TX delay = %ums", 10 * s->ch_params.tx_delay); in do_kiss_params() 356 s->hdlctx.numflags = tenms_to_2flags(s, s->ch_params.tx_delay); in start_tx() 509 bi.data.cp.tx_delay = s->ch_params.tx_delay; in hdlcdrv_siocdevprivate() 519 s->ch_params.tx_delay = bi.data.cp.tx_delay; in hdlcdrv_siocdevprivate()
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| A D | 6pack.c | 105 unsigned char tx_delay; member 184 count = encode_sixpack(p, sp->xbuff, len, sp->tx_delay); in sp_encaps() 188 case 1: sp->tx_delay = p[1]; in sp_encaps() 591 sp->tx_delay = SIXP_TXDELAY; in sixpack_open() 766 int length, unsigned char tx_delay) in encode_sixpack() argument 775 buf[0] = tx_delay; in encode_sixpack()
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| A D | baycom_epp.c | 331 bc->ch_params.tx_delay = data[1]; in do_kiss_params() 332 PKP("TX delay = %ums", 10 * bc->ch_params.tx_delay); in do_kiss_params() 447 bc->hdlctx.flags = tenms_to_flags(bc, bc->ch_params.tx_delay); in transmit() 1018 hi.data.cp.tx_delay = bc->ch_params.tx_delay; in baycom_siocdevprivate() 1028 bc->ch_params.tx_delay = hi.data.cp.tx_delay; in baycom_siocdevprivate()
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| /drivers/net/dsa/sja1105/ |
| A D | sja1105_clocking.c | 519 int tx_delay = priv->rgmii_tx_delay_ps[port]; in sja1105pqrs_setup_rgmii_delay() local 525 if (tx_delay) in sja1105pqrs_setup_rgmii_delay() 526 pad_mii_id.txc_delay = SJA1105_RGMII_DELAY_PS_TO_HW(tx_delay); in sja1105pqrs_setup_rgmii_delay() 545 if (tx_delay) { in sja1105pqrs_setup_rgmii_delay() 561 int tx_delay = priv->rgmii_tx_delay_ps[port]; in sja1110_setup_rgmii_delay() local 574 if (tx_delay) { in sja1110_setup_rgmii_delay() 575 pad_mii_id.txc_delay = SJA1105_RGMII_DELAY_PS_TO_HW(tx_delay); in sja1110_setup_rgmii_delay()
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| A D | sja1105_main.c | 1136 int rx_delay = -1, tx_delay = -1; in sja1105_parse_rgmii_delays() local 1142 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); in sja1105_parse_rgmii_delays() 1144 if (rx_delay == -1 && tx_delay == -1 && priv->fixed_link[port]) { in sja1105_parse_rgmii_delays() 1157 tx_delay = 2000; in sja1105_parse_rgmii_delays() 1162 if (tx_delay < 0) in sja1105_parse_rgmii_delays() 1163 tx_delay = 0; in sja1105_parse_rgmii_delays() 1165 if ((rx_delay || tx_delay) && !priv->info->setup_rgmii_delay) { in sja1105_parse_rgmii_delays() 1171 (tx_delay && tx_delay < SJA1105_RGMII_DELAY_MIN_PS) || in sja1105_parse_rgmii_delays() 1173 (tx_delay > SJA1105_RGMII_DELAY_MAX_PS)) { in sja1105_parse_rgmii_delays() 1181 priv->rgmii_tx_delay_ps[port] = tx_delay; in sja1105_parse_rgmii_delays()
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| /drivers/staging/octeon/ |
| A D | ethernet.c | 646 bool tx_delay; in cvm_set_rgmii_delay() local 652 tx_delay = true; in cvm_set_rgmii_delay() 660 tx_delay = delay_value > 0; in cvm_set_rgmii_delay() 663 if (!rx_delay && !tx_delay) in cvm_set_rgmii_delay() 667 else if (!tx_delay) in cvm_set_rgmii_delay()
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| /drivers/phy/microchip/ |
| A D | lan966x_serdes.c | 400 bool tx_delay = false; in lan966x_rgmii_setup() local 420 tx_delay = true; in lan966x_rgmii_setup() 434 HSIO_DLL_CFG_DLL_ENA_SET(tx_delay), in lan966x_rgmii_setup() 439 lan_rmw(HSIO_DLL_CFG_DELAY_ENA_SET(tx_delay), in lan966x_rgmii_setup()
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| /drivers/net/phy/ |
| A D | nxp-c45-tja11xx.h | 25 u32 tx_delay; member
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| A D | nxp-c45-tja11xx.c | 1454 u64 tx_delay = priv->tx_delay; in nxp_c45_set_delays() local 1460 degree = div_u64(tx_delay, PS_PER_DEGREE); in nxp_c45_set_delays() 1488 &priv->tx_delay); in nxp_c45_get_delays() 1490 priv->tx_delay = DEFAULT_ID_PS; in nxp_c45_get_delays() 1492 ret = nxp_c45_check_delay(phydev, priv->tx_delay); in nxp_c45_get_delays()
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| /drivers/isdn/mISDN/ |
| A D | dsp_cmx.c | 1754 if (delay < dsp->tx_delay[0]) 1755 dsp->tx_delay[0] = delay; 1790 delay = dsp->tx_delay[0]; 1793 if (delay > dsp->tx_delay[i]) 1794 delay = dsp->tx_delay[i]; 1824 dsp->tx_delay[i] = dsp->tx_delay[i - 1]; 1827 dsp->tx_delay[0] = CMX_BUFF_HALF; /* (infinite) delay */
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| A D | dsp.h | 203 int tx_delay[MAX_SECONDS_JITTER_CHECK]; member
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| /drivers/net/ethernet/apm/xgene/ |
| A D | xgene_enet_main.h | 233 u8 tx_delay; member
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| A D | xgene_enet_hw.c | 484 CFG_TXCLK_MUXSEL0_SET(&rgmii, pdata->tx_delay); in xgene_gmac_set_speed()
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| A D | xgene_enet_main.c | 1586 pdata->tx_delay = 4; in xgene_get_tx_delay() 1595 pdata->tx_delay = delay; in xgene_get_tx_delay()
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| /drivers/net/phy/mscc/ |
| A D | mscc_main.c | 536 s32 tx_delay; in vsc85xx_update_rgmii_cntl() local 561 tx_delay = phy_get_internal_delay(phydev, vsc85xx_internal_delay, in vsc85xx_update_rgmii_cntl() 563 if (tx_delay < 0) { in vsc85xx_update_rgmii_cntl() 566 tx_delay = RGMII_CLK_DELAY_2_0_NS; in vsc85xx_update_rgmii_cntl() 568 tx_delay = RGMII_CLK_DELAY_0_2_NS; in vsc85xx_update_rgmii_cntl() 572 reg_val |= tx_delay << rgmii_tx_delay_pos; in vsc85xx_update_rgmii_cntl()
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| /drivers/net/dsa/ |
| A D | vitesse-vsc73xx-core.c | 789 u32 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS; in vsc73xx_configure_rgmii_port_delay() local 799 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_NONE; in vsc73xx_configure_rgmii_port_delay() 802 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_4_NS; in vsc73xx_configure_rgmii_port_delay() 805 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_7_NS; in vsc73xx_configure_rgmii_port_delay() 844 tx_delay | rx_delay); in vsc73xx_configure_rgmii_port_delay()
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| A D | mt7530.c | 1021 u8 tx_delay = 0; in mt7530_setup_port5() local 1059 tx_delay = 4; /* n * 0.5 ns */ in mt7530_setup_port5() 1063 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); in mt7530_setup_port5()
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| /drivers/net/dsa/realtek/ |
| A D | rtl8365mb.c | 876 int tx_delay = 0; in rtl8365mb_ext_config_rgmii() local 913 tx_delay = val / 2; in rtl8365mb_ext_config_rgmii() 933 FIELD_PREP(RTL8365MB_EXT_RGMXF_TXDELAY_MASK, tx_delay) | in rtl8365mb_ext_config_rgmii()
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| /drivers/net/dsa/microchip/ |
| A D | ksz_common.c | 5068 int rx_delay = -1, tx_delay = -1; in ksz_parse_rgmii_delay() local 5074 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); in ksz_parse_rgmii_delay() 5076 if (rx_delay == -1 && tx_delay == -1) { in ksz_parse_rgmii_delay() 5089 tx_delay = 2000; in ksz_parse_rgmii_delay() 5094 if (tx_delay < 0) in ksz_parse_rgmii_delay() 5095 tx_delay = 0; in ksz_parse_rgmii_delay() 5098 dev->ports[port_num].rgmii_tx_val = tx_delay; in ksz_parse_rgmii_delay()
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