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Searched refs:txdctl (Results 1 – 13 of 13) sorted by relevance

/drivers/net/ethernet/wangxun/libwx/
A Dwx_vf_lib.c111 u32 txdctl = 0; in wx_configure_tx_ring_vf() local
132 txdctl |= WX_VXTXDCTL_BUFLEN(wx_buf_len(ring->count)); in wx_configure_tx_ring_vf()
133 txdctl |= WX_VXTXDCTL_ENABLE; in wx_configure_tx_ring_vf()
139 wr32(wx, WX_VXTXDCTL(reg_idx), txdctl); in wx_configure_tx_ring_vf()
141 ret = read_poll_timeout(rd32, txdctl, txdctl & WX_VXTXDCTL_ENABLE, in wx_configure_tx_ring_vf()
A Dwx_hw.c1876 u32 txdctl = WX_PX_TR_CFG_ENABLE; in wx_configure_tx_ring() local
1894 txdctl |= ring->count / 128 << WX_PX_TR_CFG_TR_SIZE_SHIFT; in wx_configure_tx_ring()
1895 txdctl |= 0x20 << WX_PX_TR_CFG_WTHRESH_SHIFT; in wx_configure_tx_ring()
1909 wr32(wx, WX_PX_TR_CFG(reg_idx), txdctl); in wx_configure_tx_ring()
1912 ret = read_poll_timeout(rd32, txdctl, txdctl & WX_PX_TR_CFG_ENABLE, in wx_configure_tx_ring()
/drivers/net/ethernet/intel/igc/
A Digc_tsn.c381 u32 txdctl; in igc_tsn_disable_offload() local
387 txdctl = rd32(IGC_TXDCTL(reg_idx)); in igc_tsn_disable_offload()
388 txdctl &= ~IGC_TXDCTL_PRIORITY_HIGH; in igc_tsn_disable_offload()
389 wr32(IGC_TXDCTL(reg_idx), txdctl); in igc_tsn_disable_offload()
470 u32 txdctl = rd32(IGC_TXDCTL(ring->reg_idx)); in igc_tsn_enable_offload() local
507 txdctl &= ~IGC_TXDCTL_PRIORITY_HIGH; in igc_tsn_enable_offload()
511 txdctl &= ~IGC_TXDCTL_PRIORITY_HIGH; in igc_tsn_enable_offload()
515 txdctl |= IGC_TXDCTL_PRIORITY_HIGH; in igc_tsn_enable_offload()
518 wr32(IGC_TXDCTL(ring->reg_idx), txdctl); in igc_tsn_enable_offload()
A Digc_main.c323 u32 txdctl; in igc_disable_tx_ring_hw() local
325 txdctl = rd32(IGC_TXDCTL(idx)); in igc_disable_tx_ring_hw()
326 txdctl &= ~IGC_TXDCTL_QUEUE_ENABLE; in igc_disable_tx_ring_hw()
327 txdctl |= IGC_TXDCTL_SWFLUSH; in igc_disable_tx_ring_hw()
328 wr32(IGC_TXDCTL(idx), txdctl); in igc_disable_tx_ring_hw()
734 u32 txdctl = 0; in igc_configure_tx_ring() local
752 txdctl |= IGC_TXDCTL_PTHRESH(8) | IGC_TXDCTL_HTHRESH(1) | in igc_configure_tx_ring()
755 wr32(IGC_TXDCTL(reg_idx), txdctl); in igc_configure_tx_ring()
/drivers/net/ethernet/intel/fm10k/
A Dfm10k_common.c479 u32 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(0)); in fm10k_get_host_state_generic() local
485 if (!(~txdctl) || !(txdctl & FM10K_TXDCTL_ENABLE)) in fm10k_get_host_state_generic()
489 if (!mac->get_host_state || !(~txdctl)) in fm10k_get_host_state_generic()
493 if (mac->tx_ready && !(txdctl & FM10K_TXDCTL_ENABLE)) { in fm10k_get_host_state_generic()
A Dfm10k_pf.c833 u32 msg[4], txdctl, txqctl, tdbal = 0, tdbah = 0; in fm10k_iov_assign_default_mac_vlan_pf() local
895 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx)); in fm10k_iov_assign_default_mac_vlan_pf()
896 for (timeout = 0; txdctl & FM10K_TXDCTL_ENABLE; timeout++) { in fm10k_iov_assign_default_mac_vlan_pf()
904 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx)); in fm10k_iov_assign_default_mac_vlan_pf()
A Dfm10k_pci.c874 u32 txdctl = BIT(FM10K_TXDCTL_MAX_TIME_SHIFT) | FM10K_TXDCTL_ENABLE; in fm10k_configure_tx_ring() local
919 fm10k_write_reg(hw, FM10K_TXDCTL(reg_idx), txdctl); in fm10k_configure_tx_ring()
934 u32 txdctl; in fm10k_enable_tx_ring() local
944 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(reg_idx)); in fm10k_enable_tx_ring()
945 } while (!(txdctl & FM10K_TXDCTL_ENABLE) && --wait_loop); in fm10k_enable_tx_ring()
/drivers/net/ethernet/intel/igbvf/
A Dnetdev.c1289 u32 txdctl, dca_txctrl; in igbvf_configure_tx() local
1292 txdctl = er32(TXDCTL(0)); in igbvf_configure_tx()
1293 ew32(TXDCTL(0), txdctl & ~E1000_TXDCTL_QUEUE_ENABLE); in igbvf_configure_tx()
1316 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; in igbvf_configure_tx()
1317 ew32(TXDCTL(0), txdctl); in igbvf_configure_tx()
1565 u32 rxdctl, txdctl; in igbvf_down() local
1580 txdctl = er32(TXDCTL(0)); in igbvf_down()
1581 ew32(TXDCTL(0), txdctl & ~E1000_TXDCTL_QUEUE_ENABLE); in igbvf_down()
/drivers/net/ethernet/intel/e1000e/
A Dich8lan.c4946 u32 ctrl_ext, txdctl, snoop, fflt_dbg; in e1000_init_hw_ich8lan() local
4995 txdctl = er32(TXDCTL(0)); in e1000_init_hw_ich8lan()
4996 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | in e1000_init_hw_ich8lan()
4998 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | in e1000_init_hw_ich8lan()
5000 ew32(TXDCTL(0), txdctl); in e1000_init_hw_ich8lan()
5001 txdctl = er32(TXDCTL(1)); in e1000_init_hw_ich8lan()
5002 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | in e1000_init_hw_ich8lan()
5004 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | in e1000_init_hw_ich8lan()
5006 ew32(TXDCTL(1), txdctl); in e1000_init_hw_ich8lan()
A Dnetdev.c2940 u32 txdctl = er32(TXDCTL(0)); in e1000_configure_tx() local
2942 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH | in e1000_configure_tx()
2953 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE; in e1000_configure_tx()
2954 ew32(TXDCTL(0), txdctl); in e1000_configure_tx()
/drivers/net/ethernet/intel/ixgbevf/
A Dixgbevf_main.c1691 u32 txdctl = IXGBE_TXDCTL_ENABLE; in ixgbevf_configure_tx_ring() local
1725 txdctl |= (8 << 16); /* WTHRESH = 8 */ in ixgbevf_configure_tx_ring()
1728 txdctl |= (1u << 8) | /* HTHRESH = 1 */ in ixgbevf_configure_tx_ring()
1738 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx), txdctl); in ixgbevf_configure_tx_ring()
1743 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(reg_idx)); in ixgbevf_configure_tx_ring()
1744 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); in ixgbevf_configure_tx_ring()
/drivers/net/ethernet/intel/ixgbe/
A Dixgbe_main.c3910 u32 txdctl = IXGBE_TXDCTL_ENABLE; in ixgbe_configure_tx_ring() local
3941 txdctl |= 1u << 16; /* WTHRESH = 1 */ in ixgbe_configure_tx_ring()
3943 txdctl |= 8u << 16; /* WTHRESH = 8 */ in ixgbe_configure_tx_ring()
3949 txdctl |= (1u << 8) | /* HTHRESH = 1 */ in ixgbe_configure_tx_ring()
3978 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); in ixgbe_configure_tx_ring()
3988 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); in ixgbe_configure_tx_ring()
6418 u32 txdctl; in ixgbe_disable_tx() local
6466 txdctl = 0; in ixgbe_disable_tx()
6486 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) in ixgbe_disable_tx()
11099 u32 txdctl; in ixgbe_disable_txr_hw() local
[all …]
/drivers/net/ethernet/intel/igb/
A Digb_main.c4390 u32 txdctl = 0; in igb_configure_tx_ring() local
4406 txdctl |= IGB_TX_PTHRESH; in igb_configure_tx_ring()
4407 txdctl |= IGB_TX_HTHRESH << 8; in igb_configure_tx_ring()
4408 txdctl |= IGB_TX_WTHRESH << 16; in igb_configure_tx_ring()
4414 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; in igb_configure_tx_ring()
4415 wr32(E1000_TXDCTL(reg_idx), txdctl); in igb_configure_tx_ring()

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