| /drivers/usb/host/ |
| A D | ehci-atmel.c | 37 struct clk *uclk; member
54 clk_prepare_enable(atmel_ehci->uclk); in atmel_start_clock()
65 clk_disable_unprepare(atmel_ehci->uclk); in atmel_stop_clock()
141 atmel_ehci->uclk = devm_clk_get(&pdev->dev, "usb_clk"); in ehci_atmel_drv_probe()
142 if (IS_ERR(atmel_ehci->uclk)) { in ehci_atmel_drv_probe()
144 retval = PTR_ERR(atmel_ehci->uclk); in ehci_atmel_drv_probe()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/ |
| A D | dml2_mcg_dcn4.c | 62 for (i = 0; i < soc_bb->clk_table.uclk.num_clk_values; i++) { in build_min_clk_table_fine_grained()
63 …tries[i].pre_derate_dram_bw_kbps = uclk_to_dram_bw_kbps(soc_bb->clk_table.uclk.clk_values_khz[i], … in build_min_clk_table_fine_grained()
67 min_table->dram_bw_table.num_entries = soc_bb->clk_table.uclk.num_clk_values; in build_min_clk_table_fine_grained()
137 for (i = 0; i < soc_bb->clk_table.uclk.num_clk_values; i++) { in build_min_clk_table_coarse_grained()
138 …tries[i].pre_derate_dram_bw_kbps = uclk_to_dram_bw_kbps(soc_bb->clk_table.uclk.clk_values_khz[i], … in build_min_clk_table_coarse_grained()
142 min_table->dram_bw_table.num_entries = soc_bb->clk_table.uclk.num_clk_values; in build_min_clk_table_coarse_grained()
158 if (soc_bb->clk_table.uclk.num_clk_values > DML_MCG_MAX_CLK_TABLE_SIZE) in build_min_clock_table()
170 soc_bb->clk_table.fclk.num_clk_values == soc_bb->clk_table.uclk.num_clk_values) in build_min_clock_table()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/ |
| A D | dml2_dpmm_dcn4.c | 23 double *uclk, in get_minimum_clocks_for_latency() argument
327 for (index = 0; index < state_table->uclk.num_clk_values; index++) { in map_soc_min_clocks_to_dpm_coarse_grained()
330 display_cfg->min_clocks.dcn4x.active.uclk_khz <= state_table->uclk.clk_values_khz[index]) { in map_soc_min_clocks_to_dpm_coarse_grained()
333 display_cfg->min_clocks.dcn4x.active.uclk_khz = state_table->uclk.clk_values_khz[index]; in map_soc_min_clocks_to_dpm_coarse_grained()
341 for (index = 0; index < state_table->uclk.num_clk_values; index++) { in map_soc_min_clocks_to_dpm_coarse_grained()
344 display_cfg->min_clocks.dcn4x.idle.uclk_khz <= state_table->uclk.clk_values_khz[index]) { in map_soc_min_clocks_to_dpm_coarse_grained()
347 display_cfg->min_clocks.dcn4x.idle.uclk_khz = state_table->uclk.clk_values_khz[index]; in map_soc_min_clocks_to_dpm_coarse_grained()
380 state_table->fclk.num_clk_values == state_table->uclk.num_clk_values) { in map_min_clocks_to_dpm()
578 ….dcn4x.active.uclk_khz = in_out->soc_bb->clk_table.uclk.clk_values_khz[in_out->soc_bb->clk_table.u… in clamp_uclk_to_max()
579 ….svp_prefetch.uclk_khz = in_out->soc_bb->clk_table.uclk.clk_values_khz[in_out->soc_bb->clk_table.u… in clamp_uclk_to_max()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| A D | dml21_translation_helper.c | 147 dml_clk_table->uclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_memclk_levels; in override_dml_init_with_values_from_smu()
149 if (i < dml_clk_table->uclk.num_clk_values) { in override_dml_init_with_values_from_smu()
153 dml_clk_table->uclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.memclk_mhz * 1000; in override_dml_init_with_values_from_smu()
154 dml_clk_table->uclk.num_clk_values = i + 1; in override_dml_init_with_values_from_smu()
156 dml_clk_table->uclk.clk_values_khz[i] = 0; in override_dml_init_with_values_from_smu()
157 dml_clk_table->uclk.num_clk_values = i; in override_dml_init_with_values_from_smu()
160 dml_clk_table->uclk.clk_values_khz[i] = dc_clk_table->entries[i].memclk_mhz * 1000; in override_dml_init_with_values_from_smu()
163 dml_clk_table->uclk.clk_values_khz[i] = 0; in override_dml_init_with_values_from_smu()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| A D | dml2_core_utils.c | 538 for (i = 0; i < clk_table->uclk.num_clk_values; i++) { in dml2_core_utils_get_active_min_uclk_dpm_index()
539 …L::%s: clk_table.uclk.clk_values_khz[%d] = %ld\n", __func__, i, clk_table->uclk.clk_values_khz[i]); in dml2_core_utils_get_active_min_uclk_dpm_index()
541 if (uclk_freq_khz == clk_table->uclk.clk_values_khz[i]) { in dml2_core_utils_get_active_min_uclk_dpm_index()
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| A D | dml2_core_dcn4.c | 533 for (i = 0; i < soc_bb->clk_table.uclk.num_clk_values; i++) { in lookup_uclk_dpm_index_by_freq()
534 if (uclk_freq_khz == soc_bb->clk_table.uclk.clk_values_khz[i]) in lookup_uclk_dpm_index_by_freq()
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| /drivers/gpu/drm/amd/pm/swsmu/smu12/ |
| A D | smu_v12_0.c | 343 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; in smu_v12_0_get_vbios_bootup_values()
360 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; in smu_v12_0_get_vbios_bootup_values()
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| A D | renoir_ppt.c | 293 clock_limit = smu->smu_table.boot_values.uclk; in renoir_get_dpm_ultimate_freq()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
| A D | dml_top_soc_parameter_types.h | 119 struct dml2_clk_table uclk; member
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/ |
| A D | dcn4_soc_bb.h | 86 .uclk = {
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| A D | dcn32_clk_mgr.c | 707 !dc->work_arounds.clock_update_disable_mask.uclk) { in dcn32_update_clocks()
747 !dc->work_arounds.clock_update_disable_mask.uclk) { in dcn32_update_clocks()
755 !dc->work_arounds.clock_update_disable_mask.uclk) { in dcn32_update_clocks()
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| /drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| A D | smu_v13_0.c | 611 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; in smu_v13_0_get_vbios_bootup_values()
625 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; in smu_v13_0_get_vbios_bootup_values()
640 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz; in smu_v13_0_get_vbios_bootup_values()
871 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100; in smu_v13_0_init_max_sustainable_clocks()
1799 *value = smu->smu_table.boot_values.uclk; in smu_v13_0_get_boot_freq_by_index()
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| A D | aldebaran_ppt.c | 452 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in aldebaran_set_default_dpm_table()
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| A D | smu_v13_0_7_ppt.c | 634 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in smu_v13_0_7_set_default_dpm_table()
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| /drivers/gpu/drm/amd/pm/swsmu/smu14/ |
| A D | smu_v14_0.c | 597 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; in smu_v14_0_get_vbios_bootup_values()
611 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; in smu_v14_0_get_vbios_bootup_values()
626 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz; in smu_v14_0_get_vbios_bootup_values()
1105 clock_limit = smu->smu_table.boot_values.uclk; in smu_v14_0_get_dpm_ultimate_freq()
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| A D | smu_v14_0_0_ppt.c | 786 clock_limit = smu->smu_table.boot_values.uclk; in smu_v14_0_1_get_dpm_ultimate_freq()
908 clock_limit = smu->smu_table.boot_values.uclk; in smu_v14_0_0_get_dpm_ultimate_freq()
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| A D | smu_v14_0_2_ppt.c | 566 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in smu_v14_0_2_set_default_dpm_table()
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| /drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| A D | smu_v11_0.c | 555 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; in smu_v11_0_get_vbios_bootup_values()
572 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; in smu_v11_0_get_vbios_bootup_values()
837 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100; in smu_v11_0_init_max_sustainable_clocks()
1721 clock_limit = smu->smu_table.boot_values.uclk; in smu_v11_0_get_dpm_ultimate_freq()
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| A D | arcturus_ppt.c | 416 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in arcturus_set_default_dpm_table()
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| A D | vangogh_ppt.c | 901 clock_limit = smu->smu_table.boot_values.uclk; in vangogh_get_dpm_ultimate_freq()
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| A D | sienna_cichlid_ppt.c | 1011 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in sienna_cichlid_set_default_dpm_table()
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| /drivers/net/ethernet/chelsio/cxgb3/ |
| A D | common.h | 357 unsigned int uclk; member
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| A D | t3_hw.c | 586 VPD_ENTRY(uclk, 6); /* uP clk */
671 ret = vpdstrtouint(vpd.uclk_data, vpd.uclk_len, 10, &p->uclk); in get_vpd_params()
3364 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params); in t3_init_hw()
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| /drivers/gpu/drm/amd/pm/swsmu/inc/ |
| A D | amdgpu_smu.h | 288 uint32_t uclk; member
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| /drivers/gpu/drm/amd/display/dc/ |
| A D | dc.h | 362 uint8_t uclk : 1; member
|