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Searched refs:uclk_pstate (Results 1 – 22 of 22) sorted by relevance

/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/
A Ddcn401_hubbub.c296 > hubbub2->watermarks.dcn4x.a.uclk_pstate) { in hubbub401_program_pstate_watermarks()
297 hubbub2->watermarks.dcn4x.a.uclk_pstate = in hubbub401_program_pstate_watermarks()
298 watermarks->dcn4x.a.uclk_pstate; in hubbub401_program_pstate_watermarks()
303 watermarks->dcn4x.a.uclk_pstate, watermarks->dcn4x.a.uclk_pstate); in hubbub401_program_pstate_watermarks()
304 } else if (watermarks->dcn4x.a.uclk_pstate in hubbub401_program_pstate_watermarks()
305 < hubbub2->watermarks.dcn4x.a.uclk_pstate) in hubbub401_program_pstate_watermarks()
311 hubbub2->watermarks.dcn4x.b.uclk_pstate = in hubbub401_program_pstate_watermarks()
312 watermarks->dcn4x.b.uclk_pstate; in hubbub401_program_pstate_watermarks()
317 watermarks->dcn4x.b.uclk_pstate, watermarks->dcn4x.b.uclk_pstate); in hubbub401_program_pstate_watermarks()
318 } else if (watermarks->dcn4x.b.uclk_pstate in hubbub401_program_pstate_watermarks()
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/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/
A Ddml2_top_soc15.c148 l->uclk_pstate.init_params.instance = &params->dml->pmo_instance; in dml2_top_optimization_init_function_uclk_pstate()
149 l->uclk_pstate.init_params.base_display_config = params->display_config; in dml2_top_optimization_init_function_uclk_pstate()
151 return params->dml->pmo_instance.init_for_uclk_pstate(&l->uclk_pstate.init_params); in dml2_top_optimization_init_function_uclk_pstate()
158 l->uclk_pstate.test_params.instance = &params->dml->pmo_instance; in dml2_top_optimization_test_function_uclk_pstate()
159 l->uclk_pstate.test_params.base_display_config = params->display_config; in dml2_top_optimization_test_function_uclk_pstate()
161 return params->dml->pmo_instance.test_for_uclk_pstate(&l->uclk_pstate.test_params); in dml2_top_optimization_test_function_uclk_pstate()
168 l->uclk_pstate.optimize_params.instance = &params->dml->pmo_instance; in dml2_top_optimization_optimize_function_uclk_pstate()
169 l->uclk_pstate.optimize_params.base_display_config = params->display_config; in dml2_top_optimization_optimize_function_uclk_pstate()
171 l->uclk_pstate.optimize_params.last_candidate_failed = !params->last_candidate_supported; in dml2_top_optimization_optimize_function_uclk_pstate()
180 l->uclk_pstate.init_params.instance = &params->dml->pmo_instance; in dml2_top_optimization_init_function_stutter()
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/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dsmu_v13_0_6_ppt.c1119 pstate_table->uclk_pstate.min = mem_table->min; in smu_v13_0_6_populate_umd_state_clk()
1134 pstate_table->uclk_pstate.standard = in smu_v13_0_6_populate_umd_state_clk()
1141 pstate_table->uclk_pstate.standard = in smu_v13_0_6_populate_umd_state_clk()
1142 pstate_table->uclk_pstate.min; in smu_v13_0_6_populate_umd_state_clk()
1427 pstate_table->uclk_pstate.curr.min, in smu_v13_0_6_print_clk_levels()
1428 pstate_table->uclk_pstate.curr.max); in smu_v13_0_6_print_clk_levels()
2065 pstate_table->uclk_pstate.curr.max = max; in smu_v13_0_6_set_soft_freq_limited_range()
2183 pstate_table->uclk_pstate.custom.max = in smu_v13_0_6_usr_edit_dpm_table()
2184 pstate_table->uclk_pstate.curr.max; in smu_v13_0_6_usr_edit_dpm_table()
2240 if (!pstate_table->uclk_pstate.custom.max) in smu_v13_0_6_usr_edit_dpm_table()
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A Daldebaran_ppt.c610 pstate_table->uclk_pstate.min = mem_table->min; in aldebaran_populate_umd_state_clk()
611 pstate_table->uclk_pstate.peak = mem_table->max; in aldebaran_populate_umd_state_clk()
612 pstate_table->uclk_pstate.curr.min = mem_table->min; in aldebaran_populate_umd_state_clk()
613 pstate_table->uclk_pstate.curr.max = mem_table->max; in aldebaran_populate_umd_state_clk()
625 pstate_table->uclk_pstate.standard = in aldebaran_populate_umd_state_clk()
632 pstate_table->uclk_pstate.standard = in aldebaran_populate_umd_state_clk()
633 pstate_table->uclk_pstate.min; in aldebaran_populate_umd_state_clk()
887 pstate_table->uclk_pstate.curr.min, in aldebaran_emit_clk_levels()
888 pstate_table->uclk_pstate.curr.max); in aldebaran_emit_clk_levels()
A Dsmu_v13_0.c1645 mclk_min = mclk_max = pstate_table->uclk_pstate.standard; in smu_v13_0_set_performance_level()
1655 mclk_min = mclk_max = pstate_table->uclk_pstate.min; in smu_v13_0_set_performance_level()
1659 mclk_min = mclk_max = pstate_table->uclk_pstate.peak; in smu_v13_0_set_performance_level()
1708 pstate_table->uclk_pstate.curr.min = mclk_min; in smu_v13_0_set_performance_level()
1709 pstate_table->uclk_pstate.curr.max = mclk_max; in smu_v13_0_set_performance_level()
2505 pstate_table->uclk_pstate.custom.min = 0; in smu_v13_0_reset_custom_level()
2506 pstate_table->uclk_pstate.custom.max = 0; in smu_v13_0_reset_custom_level()
A Dsmu_v13_0_7_ppt.c2317 pstate_table->uclk_pstate.min = mem_table->min; in smu_v13_0_7_populate_umd_state_clk()
2318 pstate_table->uclk_pstate.peak = mem_table->max; in smu_v13_0_7_populate_umd_state_clk()
2337 pstate_table->uclk_pstate.standard = mem_table->max; in smu_v13_0_7_populate_umd_state_clk()
A Dsmu_v13_0_0_ppt.c2331 pstate_table->uclk_pstate.min = mem_table->min; in smu_v13_0_0_populate_umd_state_clk()
2332 pstate_table->uclk_pstate.peak = mem_table->max; in smu_v13_0_0_populate_umd_state_clk()
2351 pstate_table->uclk_pstate.standard = mem_table->max; in smu_v13_0_0_populate_umd_state_clk()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/
A Ddml2_internal_shared_types.h808 } uclk_pstate; member
830 } uclk_pstate; member
847 } uclk_pstate; member
/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
A Ddml_top_dchub_registers.h162 uint32_t uclk_pstate; member
A Ddml_top_display_cfg_types.h420 enum dml2_twait_budgeting_setting uclk_pstate; member
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/
A Ddml2_pmo_dcn3.c549 …stream_descriptor->overrides.hw.twait_budgeting.uclk_pstate == dml2_twait_budgeting_setting_if_nee… in pmo_dcn3_init_for_pstate_support()
552 …if (stream_descriptor->overrides.hw.twait_budgeting.uclk_pstate == dml2_twait_budgeting_setting_tr… in pmo_dcn3_init_for_pstate_support()
/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Darcturus_ppt.c587 pstate_table->uclk_pstate.min = mem_table->min; in arcturus_populate_umd_state_clk()
588 pstate_table->uclk_pstate.peak = mem_table->max; in arcturus_populate_umd_state_clk()
598 pstate_table->uclk_pstate.standard = in arcturus_populate_umd_state_clk()
605 pstate_table->uclk_pstate.standard = in arcturus_populate_umd_state_clk()
606 pstate_table->uclk_pstate.min; in arcturus_populate_umd_state_clk()
A Dsienna_cichlid_ppt.c1502 pstate_table->uclk_pstate.min = mem_table->min; in sienna_cichlid_populate_umd_state_clk()
1503 pstate_table->uclk_pstate.peak = mem_table->max; in sienna_cichlid_populate_umd_state_clk()
1512 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK; in sienna_cichlid_populate_umd_state_clk()
1517 pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK; in sienna_cichlid_populate_umd_state_clk()
1522 pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK; in sienna_cichlid_populate_umd_state_clk()
A Dsmu_v11_0.c1894 mclk_min = mclk_max = pstate_table->uclk_pstate.standard; in smu_v11_0_set_performance_level()
1901 mclk_min = mclk_max = pstate_table->uclk_pstate.min; in smu_v11_0_set_performance_level()
1905 mclk_min = mclk_max = pstate_table->uclk_pstate.peak; in smu_v11_0_set_performance_level()
A Dnavi10_ppt.c1773 pstate_table->uclk_pstate.min = mem_table->min; in navi10_populate_umd_state_clk()
1774 pstate_table->uclk_pstate.peak = mem_table->max; in navi10_populate_umd_state_clk()
1784 pstate_table->uclk_pstate.standard = in navi10_populate_umd_state_clk()
1791 pstate_table->uclk_pstate.standard = in navi10_populate_umd_state_clk()
1792 pstate_table->uclk_pstate.min; in navi10_populate_umd_state_clk()
/drivers/gpu/drm/amd/pm/swsmu/smu14/
A Dsmu_v14_0.c1308 mclk_min = mclk_max = pstate_table->uclk_pstate.standard; in smu_v14_0_set_performance_level()
1318 mclk_min = mclk_max = pstate_table->uclk_pstate.min; in smu_v14_0_set_performance_level()
1322 mclk_min = mclk_max = pstate_table->uclk_pstate.peak; in smu_v14_0_set_performance_level()
1358 pstate_table->uclk_pstate.curr.min = mclk_min; in smu_v14_0_set_performance_level()
1359 pstate_table->uclk_pstate.curr.max = mclk_max; in smu_v14_0_set_performance_level()
A Dsmu_v14_0_2_ppt.c1611 pstate_table->uclk_pstate.min = mem_table->min; in smu_v14_0_2_populate_umd_state_clk()
1612 pstate_table->uclk_pstate.peak = mem_table->max; in smu_v14_0_2_populate_umd_state_clk()
1631 pstate_table->uclk_pstate.standard = mem_table->max; in smu_v14_0_2_populate_umd_state_clk()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/
A Ddml2_dpmm_dcn4.c757 …dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].uclk_pstate = (int unsigned)(mode_lib->mp.Water… in dpmm_dcn4_map_watermarks()
773 …dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_B].uclk_pstate = (int unsigned)(mode_lib->mp.Water… in dpmm_dcn4_map_watermarks()
/drivers/gpu/drm/amd/pm/swsmu/inc/
A Damdgpu_smu.h478 struct pstates_clk_freq uclk_pstate; member
/drivers/gpu/drm/amd/pm/swsmu/
A Damdgpu_smu.c3125 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; in smu_read_sensor()
3133 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; in smu_read_sensor()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_translation_helper.c1106 …eam_descriptors[disp_cfg_stream_location].overrides.hw.twait_budgeting.uclk_pstate = dml2_twait_bu… in dml21_map_dc_state_into_dml_display_cfg()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
A Ddml2_core_dcn4_calcs.c12164 …wm_regs->uclk_pstate = (int unsigned)(mode_lib->mp.Watermark.DRAMClockChangeWatermark * refclk_fre… in rq_dlg_get_wm_regs()

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