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Searched refs:ucode (Results 1 – 25 of 90) sorted by relevance

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/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
A Ducode_loader.c94 void brcms_ucode_data_free(struct brcms_ucode *ucode) in brcms_ucode_data_free() argument
97 brcms_ucode_free_buf((void *)ucode->d11lcn0initvals24); in brcms_ucode_data_free()
99 brcms_ucode_free_buf((void *)ucode->d11lcn1initvals24); in brcms_ucode_data_free()
101 brcms_ucode_free_buf((void *)ucode->d11lcn2initvals24); in brcms_ucode_data_free()
102 brcms_ucode_free_buf((void *)ucode->d11n0absinitvals16); in brcms_ucode_data_free()
103 brcms_ucode_free_buf((void *)ucode->d11n0bsinitvals16); in brcms_ucode_data_free()
104 brcms_ucode_free_buf((void *)ucode->d11n0initvals16); in brcms_ucode_data_free()
105 brcms_ucode_free_buf((void *)ucode->bcm43xx_16_mimo); in brcms_ucode_data_free()
106 brcms_ucode_free_buf((void *)ucode->bcm43xx_24_lcn); in brcms_ucode_data_free()
107 brcms_ucode_free_buf((void *)ucode->bcm43xx_bommajor); in brcms_ucode_data_free()
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A Ducode_loader.h46 int brcms_ucode_data_init(struct brcms_info *wl, struct brcms_ucode *ucode);
48 void brcms_ucode_data_free(struct brcms_ucode *ucode);
/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_ucode.c842 if (!ucode->fw) in amdgpu_ucode_init_single_fw()
845 ucode->mc_addr = mc_addr; in amdgpu_ucode_init_single_fw()
846 ucode->kaddr = kptr; in amdgpu_ucode_init_single_fw()
864 switch (ucode->ucode_id) { in amdgpu_ucode_init_single_fw()
980 ucode->ucode_size = ucode->fw->size; in amdgpu_ucode_init_single_fw()
984 ucode->ucode_size = ucode->fw->size; in amdgpu_ucode_init_single_fw()
1085 memcpy(ucode->kaddr, ucode_addr, ucode->ucode_size); in amdgpu_ucode_init_single_fw()
1098 if (!ucode->fw) in amdgpu_ucode_patch_jt()
1103 dst_addr = ucode->kaddr + in amdgpu_ucode_patch_jt()
1167 ucode = &adev->firmware.ucode[i]; in amdgpu_ucode_init_bo()
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A Damdgpu_cgs.c213 struct amdgpu_firmware_info *ucode; in amdgpu_cgs_get_firmware_info() local
219 ucode = &adev->firmware.ucode[id]; in amdgpu_cgs_get_firmware_info()
220 if (ucode->fw == NULL) in amdgpu_cgs_get_firmware_info()
223 gpu_addr = ucode->mc_addr; in amdgpu_cgs_get_firmware_info()
224 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; in amdgpu_cgs_get_firmware_info()
233 info->kptr = ucode->kaddr; in amdgpu_cgs_get_firmware_info()
251 struct amdgpu_firmware_info *ucode = NULL; in amdgpu_cgs_get_firmware_info() local
366 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; in amdgpu_cgs_get_firmware_info()
367 ucode->ucode_id = AMDGPU_UCODE_ID_SMC; in amdgpu_cgs_get_firmware_info()
368 ucode->fw = adev->pm.fw; in amdgpu_cgs_get_firmware_info()
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A Damdgpu_rlc.c332 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; in amdgpu_gfx_rlc_init_microcode_v2_0()
368 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; in amdgpu_gfx_rlc_init_microcode_v2_1()
406 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; in amdgpu_gfx_rlc_init_microcode_v2_2()
414 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; in amdgpu_gfx_rlc_init_microcode_v2_2()
441 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_P]; in amdgpu_gfx_rlc_init_microcode_v2_3()
449 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_V]; in amdgpu_gfx_rlc_init_microcode_v2_3()
477 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS]; in amdgpu_gfx_rlc_init_microcode_v2_4()
485 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE0_TAP_DELAYS]; in amdgpu_gfx_rlc_init_microcode_v2_4()
493 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE1_TAP_DELAYS]; in amdgpu_gfx_rlc_init_microcode_v2_4()
501 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE2_TAP_DELAYS]; in amdgpu_gfx_rlc_init_microcode_v2_4()
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A Dsmu_v13_0_10.c144 struct amdgpu_firmware_info *ucode; in smu_v13_0_10_mode2_restore_ip() local
149 ucode = &adev->firmware.ucode[i]; in smu_v13_0_10_mode2_restore_ip()
151 switch (ucode->ucode_id) { in smu_v13_0_10_mode2_restore_ip()
154 ucode_list[ucode_count++] = ucode; in smu_v13_0_10_mode2_restore_ip()
A Damdgpu_psp.c743 if (ucode) in psp_cmd_submit_buf()
746 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); in psp_cmd_submit_buf()
764 if (ucode) { in psp_cmd_submit_buf()
2623 switch (ucode->ucode_id) { in psp_get_fw_type()
2846 switch (ucode->ucode_id) { in psp_print_fw_hdr()
2989 if (!ucode->fw || !ucode->ucode_size) in fw_load_skip_check()
3018 struct amdgpu_firmware_info *ucode; in psp_load_fw_list() local
3021 ucode = ucode_list[i]; in psp_load_fw_list()
3022 psp_print_fw_hdr(psp, ucode); in psp_load_fw_list()
3047 ucode = &adev->firmware.ucode[i]; in psp_load_non_psp_fw()
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A Daldebaran.c215 struct amdgpu_firmware_info *ucode; in aldebaran_mode2_restore_ip() local
223 ucode = &adev->firmware.ucode[i]; in aldebaran_mode2_restore_ip()
224 if (!ucode->fw) in aldebaran_mode2_restore_ip()
226 switch (ucode->ucode_id) { in aldebaran_mode2_restore_ip()
241 ucode_list[ucode_count++] = ucode; in aldebaran_mode2_restore_ip()
A Damdgpu_mes.c590 int ucode, ucode_data; in amdgpu_mes_init_microcode() local
593 ucode = AMDGPU_UCODE_ID_CP_MES; in amdgpu_mes_init_microcode()
596 ucode = AMDGPU_UCODE_ID_CP_MES1; in amdgpu_mes_init_microcode()
600 info = &adev->firmware.ucode[ucode]; in amdgpu_mes_init_microcode()
601 info->ucode_id = ucode; in amdgpu_mes_init_microcode()
607 info = &adev->firmware.ucode[ucode_data]; in amdgpu_mes_init_microcode()
/drivers/crypto/marvell/octeontx/
A Dotx_cptpf_ucode.c396 curr->ucode.ver_num.nn, curr->ucode.ver_num.xx, in print_tar_dbg_info()
397 curr->ucode.ver_num.yy, curr->ucode.ver_num.zz); in print_tar_dbg_info()
565 ucode->ver_num.xx, ucode->ver_num.yy, ucode->ver_num.zz); in print_ucode_dbg_info()
835 ucode->va, ucode->dma); in ucode_unload()
856 ucode->va = dma_alloc_coherent(dev, ucode->size + in copy_ucode_to_dma_mem()
913 ucode->filename, ucode->type); in ucode_load()
957 eng_grp->engs[i].ucode = &eng_grp->ucode[0]; in disable_eng_grp()
1197 ucode = &eng_grp->g->grp[eng_grp->mirror.idx].ucode[0]; in update_ucode_ptrs()
1199 ucode = &eng_grp->ucode[0]; in update_ucode_ptrs()
1201 eng_grp->engs[0].ucode = ucode; in update_ucode_ptrs()
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A Dotx_cptpf_mbox.c140 struct otx_cpt_ucode *ucode; in otx_cpt_bind_vq_to_grp() local
165 ucode = &eng_grp->g->grp[eng_grp->mirror.idx].ucode[0]; in otx_cpt_bind_vq_to_grp()
167 ucode = &eng_grp->ucode[0]; in otx_cpt_bind_vq_to_grp()
169 if (otx_cpt_uc_supports_eng_type(ucode, OTX_CPT_SE_TYPES)) in otx_cpt_bind_vq_to_grp()
171 else if (otx_cpt_uc_supports_eng_type(ucode, OTX_CPT_AE_TYPES)) in otx_cpt_bind_vq_to_grp()
A Dotx_cptpf_ucode.h97 struct otx_cpt_ucode ucode;/* microcode information */ member
115 struct otx_cpt_ucode *ucode; /* ucode used by these engines */ member
141 struct otx_cpt_ucode ucode[OTX_CPT_MAX_ETYPES_PER_GRP]; member
176 int otx_cpt_uc_supports_eng_type(struct otx_cpt_ucode *ucode, int eng_type);
/drivers/crypto/marvell/octeontx2/
A Dotx2_cptpf_ucode.c448 curr->ucode.ver_num.nn, curr->ucode.ver_num.xx, in print_uc_info()
449 curr->ucode.ver_num.yy, curr->ucode.ver_num.zz); in print_uc_info()
678 if (ucode->va) { in ucode_unload()
701 if (!ucode->va) in copy_ucode_to_dma_mem()
751 eng_grp->engs[i].ucode = &eng_grp->ucode[0]; in disable_eng_grp()
967 ucode = &eng_grp->g->grp[eng_grp->mirror.idx].ucode[0]; in update_ucode_ptrs()
969 ucode = &eng_grp->ucode[0]; in update_ucode_ptrs()
971 eng_grp->engs[0].ucode = ucode; in update_ucode_ptrs()
975 eng_grp->engs[1].ucode = &eng_grp->ucode[1]; in update_ucode_ptrs()
977 eng_grp->engs[1].ucode = ucode; in update_ucode_ptrs()
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A Dotx2_cptpf_ucode.h90 struct otx2_cpt_ucode ucode;/* microcode information */ member
110 struct otx2_cpt_ucode *ucode; /* ucode used by these engines */ member
135 struct otx2_cpt_ucode ucode[OTX2_CPT_MAX_ETYPES_PER_GRP]; member
/drivers/soc/fsl/qe/
A Dqe.c406 const struct qe_microcode *ucode) in qe_upload_microcode() argument
408 const __be32 *code = base + be32_to_cpu(ucode->code_offset); in qe_upload_microcode()
411 if (ucode->major || ucode->minor || ucode->revision) in qe_upload_microcode()
414 ucode->id, ucode->major, ucode->minor, ucode->revision); in qe_upload_microcode()
417 "uploading microcode '%s'\n", ucode->id); in qe_upload_microcode()
423 for (i = 0; i < be32_to_cpu(ucode->count); i++) in qe_upload_microcode()
535 const struct qe_microcode *ucode = &firmware->microcode[i]; in qe_upload_firmware() local
538 if (ucode->code_offset) in qe_upload_firmware()
539 qe_upload_microcode(firmware, ucode); in qe_upload_firmware()
543 u32 trap = be32_to_cpu(ucode->traps[j]); in qe_upload_firmware()
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/drivers/crypto/cavium/nitrox/
A Dnitrox_main.c59 struct ucode { struct
113 struct ucode *ucode; in nitrox_load_fw() local
131 ucode = (struct ucode *)fw->data; in nitrox_load_fw()
133 ucode_size = be32_to_cpu(ucode->code_size) * 2; in nitrox_load_fw()
140 ucode_data = ucode->code; in nitrox_load_fw()
143 memcpy(&ndev->hw.fw_name[0][0], ucode->version, (VERSION_LEN - 2)); in nitrox_load_fw()
182 ucode = (struct ucode *)fw->data; in nitrox_load_fw()
184 ucode_size = be32_to_cpu(ucode->code_size) * 2; in nitrox_load_fw()
191 ucode_data = ucode->code; in nitrox_load_fw()
194 memcpy(&ndev->hw.fw_name[1][0], ucode->version, (VERSION_LEN - 2)); in nitrox_load_fw()
/drivers/input/touchscreen/
A Dhideep.c444 val = be32_to_cpu(ucode[0]); in hideep_program_page()
448 ucode, xfer_count); in hideep_program_page()
450 val = be32_to_cpu(ucode[xfer_count - 1]); in hideep_program_page()
482 xfer_count = xfer_len / sizeof(*ucode); in hideep_program_nvm()
496 ucode, xfer_count); in hideep_program_nvm()
507 ucode += xfer_count; in hideep_program_nvm()
528 xfer_count = xfer_len / sizeof(*ucode); in hideep_verify_nvm()
540 const u8 *ucode_bytes = (const u8 *)ucode; in hideep_verify_nvm()
554 ucode += xfer_count; in hideep_verify_nvm()
612 const __be32 *ucode, size_t ucode_len) in hideep_flash_firmware() argument
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/drivers/gpu/nova-core/firmware/
A Dfwsec.rs202 ucode: FirmwareDmaObject<Self, Signed>, field
246 &self.ucode.0 in deref()
257 let ucode = bios.fwsec_image().ucode(dev, desc)?; in new_fwsec()
258 let mut dma_object = DmaObject::from_data(dev, ucode)?; in new_fwsec()
395 ucode: ucode_signed, in new()
/drivers/net/wireless/intel/iwlwifi/
A Diwl-drv.c600 build = le32_to_cpu(ucode->u.v2.build); in iwl_parse_v1_v2_firmware()
602 le32_to_cpu(ucode->u.v2.inst_size)); in iwl_parse_v1_v2_firmware()
609 src = ucode->u.v2.data; in iwl_parse_v1_v2_firmware()
628 src = ucode->u.v1.data; in iwl_parse_v1_v2_firmware()
796 if (len < sizeof(*ucode)) { in iwl_parse_tlv_firmware()
803 le32_to_cpu(ucode->magic)); in iwl_parse_tlv_firmware()
810 build = le32_to_cpu(ucode->build); in iwl_parse_tlv_firmware()
826 data = ucode->data; in iwl_parse_tlv_firmware()
828 len -= sizeof(*ucode); in iwl_parse_tlv_firmware()
1593 const struct iwl_ucode_header *ucode; in iwl_req_fw_callback() local
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/drivers/gpu/drm/nouveau/nvkm/engine/gr/
A Dctxnv40.h13 u32 *ucode; member
27 u32 *ctxprog = ctx->ucode; in cp_out()
61 u32 *ctxprog = ctx->ucode; in cp_name()
A Dgf110.c107 .fecs.ucode = &gf100_gr_fecs_ucode,
109 .gpccs.ucode = &gf100_gr_gpccs_ucode,
A Dgf104.c135 .fecs.ucode = &gf100_gr_fecs_ucode,
137 .gpccs.ucode = &gf100_gr_gpccs_ucode,
A Dgk110b.c126 .fecs.ucode = &gk110_gr_fecs_ucode,
128 .gpccs.ucode = &gk110_gr_gpccs_ucode,
A Dgf108.c133 .fecs.ucode = &gf100_gr_fecs_ucode,
135 .gpccs.ucode = &gf100_gr_gpccs_ucode,
A Dgf119.c198 .fecs.ucode = &gf100_gr_fecs_ucode,
200 .gpccs.ucode = &gf100_gr_gpccs_ucode,

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