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Searched refs:umc_reg_offset (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
A Dumc_v6_1.c95 uint32_t umc_reg_offset) in umc_v6_1_clear_error_count_per_channel() argument
120 umc_reg_offset) * 4); in umc_v6_1_clear_error_count_per_channel()
133 umc_reg_offset) * 4); in umc_v6_1_clear_error_count_per_channel()
149 uint32_t umc_reg_offset = 0; in umc_v6_1_clear_error_count() local
162 umc_reg_offset); in umc_v6_1_clear_error_count()
261 uint32_t umc_reg_offset = 0; in umc_v6_1_query_ras_error_count() local
278 umc_reg_offset, in umc_v6_1_query_ras_error_count()
281 umc_reg_offset, in umc_v6_1_query_ras_error_count()
297 uint32_t umc_reg_offset, in umc_v6_1_query_error_address() argument
360 uint32_t umc_reg_offset = 0; in umc_v6_1_query_ras_error_address() local
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A Dumc_v6_7.c100 uint32_t umc_reg_offset; in umc_v6_7_ecc_info_query_correctable_error_count() local
142 uint32_t umc_reg_offset; in umc_v6_7_ecc_info_querry_uncorrectable_error_count() local
367 uint32_t umc_reg_offset = in umc_v6_7_reset_error_count_per_channel() local
392 umc_reg_offset) * 4); in umc_v6_7_reset_error_count_per_channel()
417 uint32_t umc_reg_offset = in umc_v6_7_query_ecc_error_count() local
421 umc_reg_offset, in umc_v6_7_query_ecc_error_count()
426 umc_reg_offset, in umc_v6_7_query_ecc_error_count()
448 uint32_t umc_reg_offset = in umc_v6_7_query_error_address() local
493 uint32_t umc_reg_offset) in umc_v6_7_query_ras_poison_mode_per_channel() argument
500 umc_reg_offset) * 4); in umc_v6_7_query_ras_poison_mode_per_channel()
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A Dumc_v8_7.c181 uint32_t umc_reg_offset) in umc_v8_7_clear_error_count_per_channel() argument
193 umc_reg_offset) * 4); in umc_v8_7_clear_error_count_per_channel()
206 umc_reg_offset) * 4); in umc_v8_7_clear_error_count_per_channel()
222 uint32_t umc_reg_offset = 0; in umc_v8_7_clear_error_count() local
230 umc_reg_offset); in umc_v8_7_clear_error_count()
308 uint32_t umc_reg_offset = 0; in umc_v8_7_query_ras_error_count() local
316 umc_reg_offset, in umc_v8_7_query_ras_error_count()
319 umc_reg_offset, in umc_v8_7_query_ras_error_count()
328 uint32_t umc_reg_offset, in umc_v8_7_query_error_address() argument
375 uint32_t umc_reg_offset = 0; in umc_v8_7_query_ras_error_address() local
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A Dumc_v8_14.c42 uint32_t umc_reg_offset = in umc_v8_14_clear_error_count_per_channel() local
49 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_14_clear_error_count_per_channel()
62 uint32_t umc_reg_offset, in umc_v8_14_query_correctable_error_count() argument
71 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v8_14_query_correctable_error_count()
78 uint32_t umc_reg_offset, in umc_v8_14_query_uncorrectable_error_count() argument
86 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v8_14_query_uncorrectable_error_count()
97 uint32_t umc_reg_offset = in umc_v8_14_query_error_count_per_channel() local
101 umc_reg_offset, in umc_v8_14_query_error_count_per_channel()
104 umc_reg_offset, in umc_v8_14_query_error_count_per_channel()
125 uint32_t umc_reg_offset = in umc_v8_14_err_cnt_init_per_channel() local
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A Dumc_v8_10.c84 uint32_t umc_reg_offset = in umc_v8_10_clear_error_count_per_channel() local
91 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_10_clear_error_count_per_channel()
104 uint32_t umc_reg_offset, in umc_v8_10_query_correctable_error_count() argument
124 uint32_t umc_reg_offset, in umc_v8_10_query_uncorrectable_error_count() argument
148 uint32_t umc_reg_offset = in umc_v8_10_query_ecc_error_count() local
152 umc_reg_offset, in umc_v8_10_query_ecc_error_count()
155 umc_reg_offset, in umc_v8_10_query_ecc_error_count()
252 uint32_t umc_reg_offset = in umc_v8_10_query_error_address() local
274 err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4); in umc_v8_10_query_error_address()
282 WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); in umc_v8_10_query_error_address()
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A Dumc_v12_0.c54 uint64_t umc_reg_offset = in umc_v12_0_reset_error_count_per_channel() local
61 WREG32_PCIE_EXT((odecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v12_0_reset_error_count_per_channel()
119 uint64_t umc_reg_offset, in umc_v12_0_query_error_count_per_type() argument
131 RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4); in umc_v12_0_query_error_count_per_type()
151 uint64_t umc_reg_offset = in umc_v12_0_query_error_count() local
154 umc_v12_0_query_error_count_per_type(adev, umc_reg_offset, in umc_v12_0_query_error_count()
156 umc_v12_0_query_error_count_per_type(adev, umc_reg_offset, in umc_v12_0_query_error_count()
158 umc_v12_0_query_error_count_per_type(adev, umc_reg_offset, in umc_v12_0_query_error_count()
335 uint64_t umc_reg_offset = in umc_v12_0_query_error_address() local
359 err_addr = RREG64_PCIE_EXT((mc_umc_addrt0 + umc_reg_offset) * 4); in umc_v12_0_query_error_address()
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