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/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calc_auto.c67 v->h_ratio[k] = v->h_ratio[k] * v->under_scan_factor; in scaler_settings_calculation()
68 v->v_ratio[k] = v->v_ratio[k] * v->under_scan_factor; in scaler_settings_calculation()
132 …v->h_ratio[k] > v->max_hscl_ratio || v->v_ratio[k] > v->max_vscl_ratio || v->h_ratio[k] > v->htaps… in mode_support_and_system_configuration()
340 …v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max5(v->vtaps[k] / 6.0 *dcn_bw_min2(… in mode_support_and_system_configuration()
747 …v->v_init_y = (v->v_ratio[k] + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k]) /… in mode_support_and_system_configuration()
802 …v->line_times_for_prefetch[k] = v->maximum_vstartup - v->urgent_latency / (v->htotal[k] / v->pixel… in mode_support_and_system_configuration()
1006 v->dcfclk = v->dcfclk_per_state[v->voltage_level]; in mode_support_and_system_configuration()
1223 v->dppclk = v->dispclk / v->dispclk_dppclk_ratio; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1393 v->v_blank_time = (v->vtotal[k] - v->vactive[k]) * v->htotal[k] / v->pixel_clock[k]; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1643 …v->dstx_after_scaler = 90.0 * v->pixel_clock[k] / v->dppclk + 42.0 * v->pixel_clock[k] / v->dispcl… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
[all …]
A Ddcn_calcs.c577 v->dcfclk = v->dcfclkv_nom0p8;
598 v->dcfclk = v->dcfclkv_max0p9;
618 v->dcfclk = v->dcfclk_per_state[v->voltage_level];
773 memset(v, 0, sizeof(*v)); in dcn_validate_bandwidth()
877 v->max_dppclk[5] = v->max_dppclk_vmax0p9; in dcn_validate_bandwidth()
878 v->max_dppclk[4] = v->max_dppclk_vmax0p9; in dcn_validate_bandwidth()
879 v->max_dppclk[3] = v->max_dppclk_vmax0p9; in dcn_validate_bandwidth()
1087 v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k]; in dcn_validate_bandwidth()
1089 v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k]; in dcn_validate_bandwidth()
1113 … dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k]; in dcn_validate_bandwidth()
[all …]
/drivers/media/platform/nxp/
A Dimx-pxp.h219 #define BF_PXP_OUT_BUF_ADDR(v) (v) argument
225 #define BF_PXP_OUT_BUF2_ADDR(v) (v) argument
388 #define BF_PXP_PS_BUF_ADDR(v) (v) argument
394 #define BF_PXP_PS_UBUF_ADDR(v) (v) argument
400 #define BF_PXP_PS_VBUF_ADDR(v) (v) argument
545 #define BF_PXP_AS_BUF_ADDR(v) (v) argument
851 #define BF_PXP_LUT_DATA_DATA(v) (v) argument
857 #define BF_PXP_LUT_EXTMEM_ADDR(v) (v) argument
863 #define BF_PXP_CFA_DATA(v) (v) argument
1491 #define BF_PXP_INIT_MEM_DATA_DATA(v) (v) argument
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddisplay_mode_vba_31.c2005 v->ReturnBusWidth * v->DCFCLKState[v->VoltageLevel][v->maxMpcComb],
2282 v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
2538 v->WritebackDelay[v->VoltageLevel][k] = v->WritebackDelay[v->VoltageLevel][j];
3099 v->MinTTUVBlank[k] = v->TCalc + v->MinTTUVBlank[k];
3162 (int) (v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]))) {
3821 || v->VRatio[k] > v->MaxVSCLRatio || v->HRatio[k] > v->htaps[k]
3871 / (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
5419 if (v->AlignedYPitch[k] > v->PitchY[k] || v->AlignedCPitch[k] > v->PitchC[k]
5537 v->SOCCLK = v->SOCCLKPerState[v->VoltageLevel];
5660 …- ((double) v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) * v->HTotal[k] / v->Pixe…
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddisplay_mode_vba_30.c1861 v->DRAMSpeedPerState[v->VoltageLevel] * v->NumberOfChannels * v->DRAMChannelWidth, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2067 …v->ReadBandwidthPlaneLuma[k] = v->SwathWidthSingleDPPY[k] * v->BytePerPixelY[k] / (v->HTotal[k] / … in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2068 …v->ReadBandwidthPlaneChroma[k] = v->SwathWidthSingleDPPC[k] * v->BytePerPixelC[k] / (v->HTotal[k] … in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2150 v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2383 v->WritebackDelay[v->VoltageLevel][k] = v->WritebackDelay[v->VoltageLevel][j]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2386 …v->MaxVStartupLines[k] = v->VTotal[k] - v->VActive[k] - dml_max(1.0, dml_ceil((double) v->Writebac… in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3977 …if (!(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1] && v->MaxDppclk[i] == v->MaxDppclk[… in dml30_ModeSupportAndSystemConfigurationFull()
4326 …v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0 / (v->HT… in dml30_ModeSupportAndSystemConfigurationFull()
4864 …v->cursor_bw_pre[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0 / (v… in dml30_ModeSupportAndSystemConfigurationFull()
5113 …if (v->AlignedYPitch[k] > v->PitchY[k] || v->AlignedCPitch[k] > v->PitchC[k] || v->AlignedDCCMetaP… in dml30_ModeSupportAndSystemConfigurationFull()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn314/
A Ddisplay_mode_vba_314.c2022 v->ReturnBusWidth * v->DCFCLKState[v->VoltageLevel][v->maxMpcComb],
2300 …v->DSCDelay[k] = v->DSCDelay[k] + (v->HTotal[k] - v->HActive[k]) * dml_ceil((double) v->DSCDelay[k…
2301 v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
2557 v->WritebackDelay[v->VoltageLevel][k] = v->WritebackDelay[v->VoltageLevel][j];
3118 v->MinTTUVBlank[k] = v->TCalc + v->MinTTUVBlank[k];
3172 …v->MIN_DST_Y_NEXT_START[k] = dml_floor((v->VTotal[k] - v->VFrontPorch[k] + v->VTotal[k] - v->VActi…
3174 …v->MIN_DST_Y_NEXT_START[k] = v->VTotal[k] - v->VFrontPorch[k] + v->VTotal[k] - v->VActive[k] - v->…
3914 || v->VRatio[k] > v->MaxVSCLRatio || v->HRatio[k] > v->htaps[k]
5505 if (v->AlignedYPitch[k] > v->PitchY[k] || v->AlignedCPitch[k] > v->PitchC[k]
5631 v->SOCCLK = v->SOCCLKPerState[v->VoltageLevel];
[all …]
/drivers/media/platform/verisilicon/
A Drockchip_vpu2_hw_h264_dec.c28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
50 #define VDPU_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(0) : 0) argument
57 #define VDPU_REG_START_CODE_E(v) ((v) ? BIT(22) : 0) argument
59 #define VDPU_REG_RLC_MODE_E(v) ((v) ? BIT(20) : 0) argument
64 #define VDPU_REG_SEQ_MBAFF_E(v) ((v) ? BIT(7) : 0) argument
73 #define VDPU_REG_REFBU_E(v) ((v) ? BIT(31) : 0) argument
[all …]
A Drockchip_vpu2_hw_mpeg2_dec.c23 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
25 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
26 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
27 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
42 #define VDPU_REG_DEC_INSWAP32_E(v) ((v) ? BIT(2) : 0) argument
43 #define VDPU_REG_DEC_OUT_ENDIAN(v) ((v) ? BIT(1) : 0) argument
44 #define VDPU_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(0) : 0) argument
51 #define VDPU_REG_RLC_MODE_E(v) ((v) ? BIT(20) : 0) argument
54 #define VDPU_REG_PIC_B_E(v) ((v) ? BIT(15) : 0) argument
64 #define VDPU_REG_ALT_SCAN_E(v) ((v) ? BIT(6) : 0) argument
[all …]
A Dhantro_g1_mpeg2_dec.c26 #define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0) argument
27 #define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0) argument
28 #define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0) argument
29 #define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0) argument
34 #define G1_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(9) : 0) argument
35 #define G1_REG_DEC_OUT_ENDIAN(v) ((v) ? BIT(8) : 0) argument
37 #define G1_REG_DEC_SCMD_DIS(v) ((v) ? BIT(5) : 0) argument
41 #define G1_REG_RLC_MODE_E(v) ((v) ? BIT(27) : 0) argument
44 #define G1_REG_PIC_B_E(v) ((v) ? BIT(21) : 0) argument
54 #define G1_REG_ALT_SCAN_E(v) ((v) ? BIT(6) : 0) argument
[all …]
/drivers/staging/media/sunxi/sun6i-isp/
A Dsun6i_isp_reg.h21 #define SUN6I_ISP_FE_CFG_SRC0_MODE(v) (((v) << 8) & GENMASK(9, 8)) argument
104 #define SUN6I_ISP_MODE_INPUT_FMT(v) ((v) & GENMASK(2, 0)) argument
106 #define SUN6I_ISP_MODE_OTF_DPC(v) (((v) << 16) & BIT(16)) argument
107 #define SUN6I_ISP_MODE_SHARP(v) (((v) << 17) & BIT(17)) argument
139 #define SUN6I_ISP_AE_SIZE_WIDTH(v) ((v) & GENMASK(10, 0)) argument
149 #define SUN6I_ISP_OB_SIZE_WIDTH(v) ((v) & GENMASK(13, 0)) argument
153 #define SUN6I_ISP_OB_VALID_WIDTH(v) ((v) & GENMASK(12, 0)) argument
202 #define SUN6I_ISP_BAYER_GAIN0_R(v) ((v) & GENMASK(11, 0)) argument
212 #define SUN6I_ISP_WB_GAIN0_R(v) ((v) & GENMASK(11, 0)) argument
216 #define SUN6I_ISP_WB_GAIN1_GB(v) ((v) & GENMASK(11, 0)) argument
[all …]
/drivers/iio/adc/
A Dstm32-dfsdm.h115 #define DFSDM_CR1_DFEN(v) FIELD_PREP(DFSDM_CR1_DFEN_MASK, v) argument
137 #define DFSDM_CR1_RCH(v) FIELD_PREP(DFSDM_CR1_RCH_MASK, v) argument
139 #define DFSDM_CR1_FAST(v) FIELD_PREP(DFSDM_CR1_FAST_MASK, v) argument
145 #define DFSDM_CR2_IE(v) FIELD_PREP(DFSDM_CR2_IE_MASK, v) argument
161 #define DFSDM_CR2_EXCH(v) FIELD_PREP(DFSDM_CR2_EXCH_MASK, v) argument
175 #define DFSDM_ISR_AWDF(v) FIELD_PREP(DFSDM_ISR_AWDF_MASK, v) argument
177 #define DFSDM_ISR_JCIP(v) FIELD_PREP(DFSDM_ISR_JCIP_MASK, v) argument
179 #define DFSDM_ISR_RCIP(v) FIELD_PREP(DFSDM_ISR_RCIP, v) argument
183 #define DFSDM_ISR_SCDF(v) FIELD_PREP(DFSDM_ISR_SCDF_MASK, v) argument
203 #define DFSDM_FCR_IOSR(v) FIELD_PREP(DFSDM_FCR_IOSR_MASK, v) argument
[all …]
/drivers/gpu/host1x/hw/
A Dhw_host1x01_uclass.h50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
86 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_base_indx_f()
92 return (v & 0xff) << 16; in host1x_uclass_wait_syncpt_base_base_indx_f()
98 return (v & 0xffff) << 0; in host1x_uclass_wait_syncpt_base_offset_f()
110 return (v & 0xff) << 24; in host1x_uclass_load_syncpt_base_base_indx_f()
122 return (v & 0xff) << 24; in host1x_uclass_incr_syncpt_base_base_indx_f()
140 return (v & 0xf) << 28; in host1x_uclass_indoff_indbe_f()
146 return (v & 0x1) << 27; in host1x_uclass_indoff_autoinc_f()
[all …]
A Dhw_host1x02_uclass.h50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
86 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_base_indx_f()
92 return (v & 0xff) << 16; in host1x_uclass_wait_syncpt_base_base_indx_f()
98 return (v & 0xffff) << 0; in host1x_uclass_wait_syncpt_base_offset_f()
110 return (v & 0xff) << 24; in host1x_uclass_load_syncpt_base_base_indx_f()
122 return (v & 0xff) << 24; in host1x_uclass_incr_syncpt_base_base_indx_f()
140 return (v & 0xf) << 28; in host1x_uclass_indoff_indbe_f()
146 return (v & 0x1) << 27; in host1x_uclass_indoff_autoinc_f()
[all …]
A Dhw_host1x06_uclass.h50 return (v & 0xff) << 10; in host1x_uclass_incr_syncpt_cond_f()
56 return (v & 0x3ff) << 0; in host1x_uclass_incr_syncpt_indx_f()
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
86 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_base_indx_f()
92 return (v & 0xff) << 16; in host1x_uclass_wait_syncpt_base_base_indx_f()
98 return (v & 0xffff) << 0; in host1x_uclass_wait_syncpt_base_offset_f()
110 return (v & 0xff) << 24; in host1x_uclass_load_syncpt_base_base_indx_f()
122 return (v & 0xff) << 24; in host1x_uclass_incr_syncpt_base_base_indx_f()
140 return (v & 0xf) << 28; in host1x_uclass_indoff_indbe_f()
146 return (v & 0x1) << 27; in host1x_uclass_indoff_autoinc_f()
[all …]
A Dhw_host1x07_uclass.h50 return (v & 0xff) << 10; in host1x_uclass_incr_syncpt_cond_f()
56 return (v & 0x3ff) << 0; in host1x_uclass_incr_syncpt_indx_f()
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
86 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_base_indx_f()
92 return (v & 0xff) << 16; in host1x_uclass_wait_syncpt_base_base_indx_f()
98 return (v & 0xffff) << 0; in host1x_uclass_wait_syncpt_base_offset_f()
110 return (v & 0xff) << 24; in host1x_uclass_load_syncpt_base_base_indx_f()
122 return (v & 0xff) << 24; in host1x_uclass_incr_syncpt_base_base_indx_f()
140 return (v & 0xf) << 28; in host1x_uclass_indoff_indbe_f()
146 return (v & 0x1) << 27; in host1x_uclass_indoff_autoinc_f()
[all …]
A Dhw_host1x08_uclass.h50 return (v & 0xff) << 10; in host1x_uclass_incr_syncpt_cond_f()
56 return (v & 0x3ff) << 0; in host1x_uclass_incr_syncpt_indx_f()
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
86 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_base_indx_f()
92 return (v & 0xff) << 16; in host1x_uclass_wait_syncpt_base_base_indx_f()
98 return (v & 0xffff) << 0; in host1x_uclass_wait_syncpt_base_offset_f()
110 return (v & 0xff) << 24; in host1x_uclass_load_syncpt_base_base_indx_f()
122 return (v & 0xff) << 24; in host1x_uclass_incr_syncpt_base_base_indx_f()
140 return (v & 0xf) << 28; in host1x_uclass_indoff_indbe_f()
146 return (v & 0x1) << 27; in host1x_uclass_indoff_autoinc_f()
[all …]
A Dhw_host1x04_uclass.h50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
86 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_base_indx_f()
92 return (v & 0xff) << 16; in host1x_uclass_wait_syncpt_base_base_indx_f()
98 return (v & 0xffff) << 0; in host1x_uclass_wait_syncpt_base_offset_f()
110 return (v & 0xff) << 24; in host1x_uclass_load_syncpt_base_base_indx_f()
122 return (v & 0xff) << 24; in host1x_uclass_incr_syncpt_base_base_indx_f()
140 return (v & 0xf) << 28; in host1x_uclass_indoff_indbe_f()
146 return (v & 0x1) << 27; in host1x_uclass_indoff_autoinc_f()
[all …]
A Dhw_host1x05_uclass.h50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
86 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_base_indx_f()
92 return (v & 0xff) << 16; in host1x_uclass_wait_syncpt_base_base_indx_f()
98 return (v & 0xffff) << 0; in host1x_uclass_wait_syncpt_base_offset_f()
110 return (v & 0xff) << 24; in host1x_uclass_load_syncpt_base_base_indx_f()
122 return (v & 0xff) << 24; in host1x_uclass_incr_syncpt_base_base_indx_f()
140 return (v & 0xf) << 28; in host1x_uclass_indoff_indbe_f()
146 return (v & 0x1) << 27; in host1x_uclass_indoff_autoinc_f()
[all …]
/drivers/md/
A Ddm-verity-target.c344 memcpy(digest, v->root_digest, v->digest_size); in verity_hash_for_block()
390 verity_io_want_digest(v, io), v->digest_size)) { in verity_recheck()
441 struct dm_verity *v = io->v; in verity_verify_io() local
543 struct dm_verity *v = io->v; in verity_finish_io() local
643 struct dm_verity *v = pw->v; in verity_prefetch_io() local
703 pw->v = v; in verity_submit_prefetch()
738 io->v = v; in verity_map()
1029 kfree(v); in verity_dtr()
1269 v->salt = kmalloc(v->salt_size, GFP_KERNEL); in verity_setup_salt_and_hashstate()
1275 hex2bin(v->salt, arg, v->salt_size)) { in verity_setup_salt_and_hashstate()
[all …]
A Ddm-verity-fec.c18 return v->fec && v->fec->dev; in verity_fec_is_enabled()
39 return offset + mod * (v->fec->rounds << v->data_dev_block_bits); in fec_interleave()
155 if (offset < v->fec->io_size && (offset + v->fec->roots) > v->fec->io_size) { in fec_decode_bufs()
193 if (unlikely(verity_hash(v, io, data, 1 << v->data_dev_block_bits, in fec_is_erasure()
231 ileaved = fec_interleave(v, rsb * v->fec->rsn + i); in fec_read_bufs()
394 r = verity_hash(v, io, fio->output, 1 << v->data_dev_block_bits, in fec_decode_rsb()
428 block = block - v->hash_start + v->data_blocks; in verity_fec_decode()
551 v->fec = NULL; in verity_fec_dtr()
653 v->fec = f; in verity_fec_ctr_alloc()
689 hash_blocks = v->hash_blocks - v->hash_start; in verity_fec_ctr()
[all …]
/drivers/gpu/drm/exynos/
A Dregs-scaler.h244 #define SCALER_SRC_WH_SET_WIDTH(v) SCALER_SET(v, 29, 16) argument
246 #define SCALER_SRC_WH_SET_HEIGHT(v) SCALER_SET(v, 13, 0) argument
268 #define SCALER_DST_WH_SET_WIDTH(v) SCALER_SET(v, 29, 16) argument
270 #define SCALER_DST_WH_SET_HEIGHT(v) SCALER_SET(v, 13, 0) argument
274 #define SCALER_DST_POS_SET_H_POS(v) SCALER_SET(v, 29, 16) argument
276 #define SCALER_DST_POS_SET_V_POS(v) SCALER_SET(v, 13, 0) argument
280 #define SCALER_H_RATIO_SET(v) SCALER_SET(v, 18, 0) argument
284 #define SCALER_V_RATIO_SET(v) SCALER_SET(v, 18, 0) argument
290 #define SCALER_ROT_CFG_SET_ROTMODE(v) SCALER_SET(v, 1, 0) argument
304 #define SCALER_CSC_COEF_SET(v) SCALER_SET(v, 11, 0) argument
[all …]
/drivers/staging/media/sunxi/cedrus/
A Dcedrus_regs.h105 ((v) ? BIT(7) : 0)
107 ((v) ? BIT(6) : 0)
109 ((v) ? BIT(5) : 0)
677 #define VE_VP8_SEGMENT3(v) SHIFT_AND_MASK_BITS(v, 31, 24) argument
678 #define VE_VP8_SEGMENT2(v) SHIFT_AND_MASK_BITS(v, 23, 16) argument
679 #define VE_VP8_SEGMENT1(v) SHIFT_AND_MASK_BITS(v, 15, 8) argument
680 #define VE_VP8_SEGMENT0(v) SHIFT_AND_MASK_BITS(v, 7, 0) argument
685 #define VE_VP8_LF_DELTA3(v) SHIFT_AND_MASK_BITS(v, 30, 24) argument
686 #define VE_VP8_LF_DELTA2(v) SHIFT_AND_MASK_BITS(v, 22, 16) argument
687 #define VE_VP8_LF_DELTA1(v) SHIFT_AND_MASK_BITS(v, 14, 8) argument
[all …]
/drivers/vhost/
A Dvdpa.c173 ops->kick_vq(v->vdpa, vq - v->vqs); in handle_vq_kick()
247 v->in_batch = 0; in vhost_vdpa_reset()
544 v->vdpa->config->set_config_cb(v->vdpa, &cb); in vhost_vdpa_set_config_call()
1270 if ((v->in_batch && v->batch_asid != asid) || !iotlb) { in vhost_vdpa_process_iotlb_msg()
1271 if (v->in_batch && v->batch_asid != asid) { in vhost_vdpa_process_iotlb_msg()
1553 kfree(v); in vhost_vdpa_release_dev()
1570 v = kzalloc(sizeof(*v), GFP_KERNEL | __GFP_RETRY_MAYFAIL); in vhost_vdpa_probe()
1571 if (!v) in vhost_vdpa_probe()
1577 kfree(v); in vhost_vdpa_probe()
1605 r = cdev_device_add(&v->cdev, &v->dev); in vhost_vdpa_probe()
[all …]
/drivers/iommu/
A Dmsm_iommu_hw-8xxx.h86 #define SET_TLBRSW(b, v) SET_GLOBAL_REG(TLBRSW, (b), (v)) argument
87 #define SET_TLBTR0(b, v) SET_GLOBAL_REG(TLBTR0, (b), (v)) argument
88 #define SET_TLBTR1(b, v) SET_GLOBAL_REG(TLBTR1, (b), (v)) argument
89 #define SET_TLBTR2(b, v) SET_GLOBAL_REG(TLBTR2, (b), (v)) argument
93 #define SET_CR(b, v) SET_GLOBAL_REG(CR, (b), (v)) argument
94 #define SET_EAR(b, v) SET_GLOBAL_REG(EAR, (b), (v)) argument
95 #define SET_ESR(b, v) SET_GLOBAL_REG(ESR, (b), (v)) argument
97 #define SET_ESYNR0(b, v) SET_GLOBAL_REG(ESYNR0, (b), (v)) argument
98 #define SET_ESYNR1(b, v) SET_GLOBAL_REG(ESYNR1, (b), (v)) argument
127 #define SET_PAR(b, c, v) SET_CTX_REG(PAR, (b), (c), (v)) argument
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddisplay_mode_vba_32.c101 v->DISPCLK_calculated = v->WritebackDISPCLK; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
138 &v->GlobalDPPCLK, v->DPPCLK); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
141 v->DPPCLK_calculated[k] = v->DPPCLK[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
196 v->SwathWidthSingleDPPY, v->SwathWidthSingleDPPC, v->SwathWidthY, v->SwathWidthC, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
206 v->ReadBandwidthSurfaceLuma[k] = v->SwathWidthSingleDPPY[k] * v->BytePerPixelY[k] in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
376 v->DSCDelay[k] = v->DSCDelay[j]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
515 v->VInitPreFillY, v->VInitPreFillC, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
842 v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1192 v, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1193 v->PrefetchModePerState[v->VoltageLevel][v->maxMpcComb], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
[all …]

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