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/drivers/staging/rtl8723bs/hal/
A DHalHWImg8723B_BB.c219 u32 v1 = Array[i]; in ODM_ReadAndConfig_MP_8723B_AGC_TAB() local
223 if (v1 < 0x40000000) { in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
233 READ_NEXT_PAIR(v1, v2, i); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
236 READ_NEXT_PAIR(v1, v2, i); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
237 READ_NEXT_PAIR(v1, v2, i); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
239 READ_NEXT_PAIR(v1, v2, i); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
241 READ_NEXT_PAIR(v1, v2, i); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
249 READ_NEXT_PAIR(v1, v2, i); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
478 u32 v1 = Array[i]; in ODM_ReadAndConfig_MP_8723B_PHY_REG() local
482 if (v1 < 0x40000000) { in ODM_ReadAndConfig_MP_8723B_PHY_REG()
[all …]
A DHalHWImg8723B_MAC.c189 u32 v1 = Array[i]; in ODM_ReadAndConfig_MP_8723B_MAC_REG() local
193 if (v1 < 0x40000000) { in ODM_ReadAndConfig_MP_8723B_MAC_REG()
194 odm_ConfigMAC_8723B(pDM_Odm, v1, (u8)v2); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
203 READ_NEXT_PAIR(v1, v2, i); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
206 READ_NEXT_PAIR(v1, v2, i); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
207 READ_NEXT_PAIR(v1, v2, i); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
209 READ_NEXT_PAIR(v1, v2, i); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
211 READ_NEXT_PAIR(v1, v2, i); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
217 READ_NEXT_PAIR(v1, v2, i); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
223 READ_NEXT_PAIR(v1, v2, i); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
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A DHalHWImg8723B_RF.c220 u32 v1 = Array[i]; in ODM_ReadAndConfig_MP_8723B_RadioA() local
224 if (v1 < 0x40000000) { in ODM_ReadAndConfig_MP_8723B_RadioA()
234 READ_NEXT_PAIR(v1, v2, i); in ODM_ReadAndConfig_MP_8723B_RadioA()
237 READ_NEXT_PAIR(v1, v2, i); in ODM_ReadAndConfig_MP_8723B_RadioA()
238 READ_NEXT_PAIR(v1, v2, i); in ODM_ReadAndConfig_MP_8723B_RadioA()
240 READ_NEXT_PAIR(v1, v2, i); in ODM_ReadAndConfig_MP_8723B_RadioA()
242 READ_NEXT_PAIR(v1, v2, i); in ODM_ReadAndConfig_MP_8723B_RadioA()
249 while (v1 < 0x40000000 && i < ArrayLen-2) in ODM_ReadAndConfig_MP_8723B_RadioA()
250 READ_NEXT_PAIR(v1, v2, i); in ODM_ReadAndConfig_MP_8723B_RadioA()
257 READ_NEXT_PAIR(v1, v2, i); in ODM_ReadAndConfig_MP_8723B_RadioA()
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/drivers/char/mwave/
A Dmwavedd.h79 #define PRINTK_2(f,s,v1) \ argument
81 printk(s,v1); \
84 #define PRINTK_3(f,s,v1,v2) \ argument
86 printk(s,v1,v2); \
116 #define PRINTK_2(f,s,v1) argument
117 #define PRINTK_3(f,s,v1,v2) argument
118 #define PRINTK_4(f,s,v1,v2,v3) argument
119 #define PRINTK_5(f,s,v1,v2,v3,v4) argument
120 #define PRINTK_6(f,s,v1,v2,v3,v4,v5) argument
121 #define PRINTK_7(f,s,v1,v2,v3,v4,v5,v6) argument
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/drivers/gpu/drm/amd/display/dc/inc/
A Dreg_helper.h69 FN(reg, f1), v1,\
74 FN(reg, f1), v1,\
80 FN(reg, f1), v1,\
88 FN(reg, f1), v1,\
97 FN(reg, f1), v1,\
107 FN(reg, f1), v1,\
118 FN(reg, f1), v1,\
130 FN(reg, f1), v1,\
143 FN(reg, f1), v1,\
236 FN(reg, f1), v1,\
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/drivers/video/fbdev/
A Datafb_iplan2p8.c113 u32 pval[4], v, v1, mask; in atafb_iplan2p8_copyarea() local
147 v1 = v & mask; in atafb_iplan2p8_copyarea()
149 pval[0] = (v ^ v1) << 8; in atafb_iplan2p8_copyarea()
151 v1 = v & mask; in atafb_iplan2p8_copyarea()
155 v1 = v & mask; in atafb_iplan2p8_copyarea()
159 v1 = v & mask; in atafb_iplan2p8_copyarea()
176 u32 pval[4], v, v1, mask; in atafb_iplan2p8_copyarea() local
210 v1 = v & mask; in atafb_iplan2p8_copyarea()
214 v1 = v & mask; in atafb_iplan2p8_copyarea()
218 v1 = v & mask; in atafb_iplan2p8_copyarea()
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A Datafb_iplan2p4.c106 u32 pval[4], v, v1, mask; in atafb_iplan2p4_copyarea() local
136 v1 = v & mask; in atafb_iplan2p4_copyarea()
137 *dst32++ = pval[0] | (v1 >> 8); in atafb_iplan2p4_copyarea()
138 pval[0] = (v ^ v1) << 8; in atafb_iplan2p4_copyarea()
140 v1 = v & mask; in atafb_iplan2p4_copyarea()
142 pval[1] = (v ^ v1) << 8; in atafb_iplan2p4_copyarea()
155 u32 pval[4], v, v1, mask; in atafb_iplan2p4_copyarea() local
185 v1 = v & mask; in atafb_iplan2p4_copyarea()
187 pval[0] = (v ^ v1) >> 8; in atafb_iplan2p4_copyarea()
189 v1 = v & mask; in atafb_iplan2p4_copyarea()
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A Datafb_iplan2p2.c106 u32 pval[4], v, v1, mask; in atafb_iplan2p2_copyarea() local
134 v1 = v & mask; in atafb_iplan2p2_copyarea()
135 *dst32++ = pval[0] | (v1 >> 8); in atafb_iplan2p2_copyarea()
136 pval[0] = (v ^ v1) << 8; in atafb_iplan2p2_copyarea()
148 u32 pval[4], v, v1, mask; in atafb_iplan2p2_copyarea() local
176 v1 = v & mask; in atafb_iplan2p2_copyarea()
177 *--dst32 = pval[0] | (v1 << 8); in atafb_iplan2p2_copyarea()
178 pval[0] = (v ^ v1) >> 8; in atafb_iplan2p2_copyarea()
/drivers/gpu/drm/amd/amdgpu/
A Dgfx_v10_3_0_cleaner_shader.asm61 v_movreld_b32 v1, 0
79 v_mbcnt_lo_u32_b32 v1, exec_hi, 0 // Set V1 to thread-ID (0..63)
80 v_mbcnt_hi_u32_b32 v1, exec_lo, v1 // Set V1 to thread-ID (0..63)
81 …v_mul_u32_u24 v1, 0x00000008, v1 // * 8, so each thread is a double-dword address (8byte)
88 ds_write2_b64 v1, v[2:3], v[2:3] offset1:32
89 ds_write2_b64 v1, v[4:5], v[4:5] offset0:64 offset1:96
90 v_add_co_u32 v1, vcc, 0x00000400, v1
A Dgfx_v11_0_3_cleaner_shader.asm56 v_movreld_b32 v1, 0
75 v_mbcnt_lo_u32_b32 v1, exec_hi, 0 // Set V1 to thread-ID (0..63)
76 v_mbcnt_hi_u32_b32 v1, exec_lo, v1 // Set V1 to thread-ID (0..63)
77 …v_mul_u32_u24 v1, 0x00000008, v1 // * 8, so each thread is a double-dword address (8byte)
84 ds_write2_b64 v1, v[2:3], v[2:3] offset1:32
85 ds_write2_b64 v1, v[4:5], v[4:5] offset0:64 offset1:96
86 v_add_co_u32 v1, vcc, 0x00000400, v1
A Dgfx_v10_1_10_cleaner_shader.asm62 v_movreld_b32 v1, 0
80 v_mbcnt_lo_u32_b32 v1, exec_hi, 0 // Set V1 to thread-ID (0..63)
81 v_mbcnt_hi_u32_b32 v1, exec_lo, v1 // Set V1 to thread-ID (0..63)
82 …v_mul_u32_u24 v1, 0x00000008, v1 // * 8, so each thread is a double-dword address (8byte)
89 ds_write2_b64 v1, v[2:3], v[2:3] offset1:32
90 ds_write2_b64 v1, v[4:5], v[4:5] offset0:64 offset1:96
91 v_add_co_u32 v1, vcc, 0x00000400, v1
A Dgfx_v9_4_3_cleaner_shader.asm67 v_mov_b32 v1, 0
89 v_mbcnt_lo_u32_b32 v1, exec_hi, 0 // Set V1 to thread-ID (0..63)
90 v_mbcnt_hi_u32_b32 v1, exec_lo, v1 // Set V1 to thread-ID (0..63)
91 …v_mul_u32_u24 v1, 0x00000008, v1 // * 8, so each thread is a double-dword address (8byt…
98 ds_write2_b64 v1, v[2:3], v[2:3] offset1:32
99 ds_write2_b64 v1, v[4:5], v[4:5] offset0:64 offset1:96
100 v_add_co_u32 v1, vcc, 0x00000400, v1
A Dgfx_v9_4_2_cleaner_shader.asm67 v_mov_b32 v1, 0
89 v_mbcnt_lo_u32_b32 v1, exec_hi, 0 // Set V1 to thread-ID (0..63)
90 v_mbcnt_hi_u32_b32 v1, exec_lo, v1 // Set V1 to thread-ID (0..63)
91 …v_mul_u32_u24 v1, 0x00000008, v1 // * 8, so each thread is a double-dword address (8byt…
98 ds_write2_b64 v1, v[2:3], v[2:3] offset1:32
99 ds_write2_b64 v1, v[4:5], v[4:5] offset0:64 offset1:96
100 v_add_co_u32 v1, vcc, 0x00000400, v1
A Datombios_encoders.c552 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; member
598 args.v1.ucAction = action; in amdgpu_atombios_encoder_setup_dig_encoder()
606 args.v1.ucLaneNum = dp_lane_count; in amdgpu_atombios_encoder_setup_dig_encoder()
608 args.v1.ucLaneNum = 8; in amdgpu_atombios_encoder_setup_dig_encoder()
610 args.v1.ucLaneNum = 4; in amdgpu_atombios_encoder_setup_dig_encoder()
825 args.v1.ucAction = action; in amdgpu_atombios_encoder_setup_dig_transmitter()
1165 args.v1.ucAction = action; in amdgpu_atombios_encoder_set_edp_panel_power()
1238 args.v1.sDigEncoder.ucEncoderMode = in amdgpu_atombios_encoder_setup_external_encoder()
1246 args.v1.sDigEncoder.ucLaneNum = 8; in amdgpu_atombios_encoder_setup_external_encoder()
1248 args.v1.sDigEncoder.ucLaneNum = 4; in amdgpu_atombios_encoder_setup_external_encoder()
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A Ddf_v4_3.c32 uint32_t v0, v1, v28, v31; in df_v4_3_query_ras_poison_mode() local
41 v1 = REG_GET_FIELD(hw_assert_msklo, in df_v4_3_query_ras_poison_mode()
48 if (v0 && v1 && v28 && v31) in df_v4_3_query_ras_poison_mode()
50 else if (!v0 && !v1 && !v28 && !v31) in df_v4_3_query_ras_poison_mode()
54 v0, v1, v28, v31); in df_v4_3_query_ras_poison_mode()
/drivers/firmware/cirrus/test/
A Dcs_dsp_mock_wmfw.c176 struct wmfw_adsp_alg_data *v1; in cs_dsp_mock_wmfw_start_alg_info_block() local
207 v1->id = cpu_to_le32(alg_id); in cs_dsp_mock_wmfw_start_alg_info_block()
209 strscpy(v1->name, name, sizeof(v1->name)); in cs_dsp_mock_wmfw_start_alg_info_block()
212 strscpy(v1->descr, description, sizeof(v1->descr)); in cs_dsp_mock_wmfw_start_alg_info_block()
267 struct wmfw_adsp_coeff_data *v1; in cs_dsp_mock_wmfw_add_coeff_desc() local
285 memset(v1, 0, sizeof(*v1)); in cs_dsp_mock_wmfw_add_coeff_desc()
288 v1->hdr.size = cpu_to_le32(bytes_needed - sizeof(v1->hdr)); in cs_dsp_mock_wmfw_add_coeff_desc()
290 v1->flags = cpu_to_le16(def->flags); in cs_dsp_mock_wmfw_add_coeff_desc()
294 strscpy(v1->name, def->fullname, sizeof(v1->name)); in cs_dsp_mock_wmfw_add_coeff_desc()
297 strscpy(v1->descr, def->description, sizeof(v1->descr)); in cs_dsp_mock_wmfw_add_coeff_desc()
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/drivers/gpu/drm/amd/display/dmub/src/
A Ddmub_reg.h65 #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \ argument
67 FN(reg, f1), v1, \
70 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ argument
72 FN(reg, f1), v1, \
78 FN(reg, f1), v1, \
92 #define REG_UPDATE_2(reg, f1, v1, f2, v2) \ argument
94 FN(reg, f1), v1,\
97 #define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3) \ argument
99 FN(reg, f1), v1, \
103 #define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ argument
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/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/
A Dlib_float_math.c69 double math_max3(double v1, double v2, double v3) in math_max3() argument
71 return v3 > math_max2(v1, v2) ? v3 : math_max2(v1, v2); in math_max3()
74 double math_max4(double v1, double v2, double v3, double v4) in math_max4() argument
76 return v4 > math_max3(v1, v2, v3) ? v4 : math_max3(v1, v2, v3); in math_max4()
79 double math_max5(double v1, double v2, double v3, double v4, double v5) in math_max5() argument
81 return math_max3(v1, v2, v3) > math_max2(v4, v5) ? math_max3(v1, v2, v3) : math_max2(v4, v5); in math_max5()
/drivers/gpu/drm/radeon/
A Datombios_encoders.c601 args.v1.ucMisc = 0; in atombios_digital_setup()
602 args.v1.ucAction = action; in atombios_digital_setup()
824 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; member
877 args.v1.ucAction = action; in atombios_dig_encoder_setup2()
885 args.v1.ucLaneNum = dp_lane_count; in atombios_dig_encoder_setup2()
887 args.v1.ucLaneNum = 8; in atombios_dig_encoder_setup2()
889 args.v1.ucLaneNum = 4; in atombios_dig_encoder_setup2()
1078 args.v1.ucAction = action; in atombios_dig_transmitter_setup2()
1398 args.v1.ucAction = action; in atombios_set_edp_panel_power()
1478 args.v1.sDigEncoder.ucLaneNum = 8; in atombios_external_encoder_setup()
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/drivers/firmware/google/
A Dmemconsole-x86-legacy.c32 } __packed v1; member
57 hdr->v1.buffer_addr, hdr->v1.start, in found_v1_header()
58 hdr->v1.end, hdr->v1.num_chars); in found_v1_header()
60 memconsole_baseaddr = phys_to_virt(hdr->v1.buffer_addr); in found_v1_header()
61 memconsole_length = hdr->v1.num_chars; in found_v1_header()
/drivers/net/wireless/ath/ath9k/
A Drng.c27 u32 v1, v2, rng_last = sc->rng_last; in ath9k_rng_data_read() local
37 v1 = REG_READ(ah, AR_PHY_TST_ADC) & 0xffff; in ath9k_rng_data_read()
41 if (v1 && v2 && rng_last != v1 && v1 != v2 && v1 != 0xffff && in ath9k_rng_data_read()
43 buf[j++] = (v1 << 16) | v2; in ath9k_rng_data_read()
/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calc_math.c94 float dcn_bw_max3(float v1, float v2, float v3) in dcn_bw_max3() argument
96 return v3 > dcn_bw_max2(v1, v2) ? v3 : dcn_bw_max2(v1, v2); in dcn_bw_max3()
99 float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5) in dcn_bw_max5() argument
101 …return dcn_bw_max3(v1, v2, v3) > dcn_bw_max2(v4, v5) ? dcn_bw_max3(v1, v2, v3) : dcn_bw_max2(v4, v… in dcn_bw_max5()
/drivers/clocksource/
A Dacpi_pm.c47 u32 v1 = 0, v2 = 0, v3 = 0; in acpi_pm_read_verified() local
56 v1 = read_pmtmr(); in acpi_pm_read_verified()
59 } while (unlikely((v1 > v2 && v1 < v3) || (v2 > v3 && v2 < v1) in acpi_pm_read_verified()
60 || (v3 > v1 && v3 < v2))); in acpi_pm_read_verified()
/drivers/net/wireless/intel/iwlwifi/mvm/
A Doffloading.c37 struct iwl_proto_offload_cmd_v1 v1; in iwl_mvm_send_proto_offload() member
148 BUILD_BUG_ON(sizeof(cmd.v1.target_ipv6_addr[0]) != in iwl_mvm_send_proto_offload()
157 memcpy(cmd.v1.target_ipv6_addr[i], in iwl_mvm_send_proto_offload()
159 sizeof(cmd.v1.target_ipv6_addr[i])); in iwl_mvm_send_proto_offload()
166 memcpy(cmd.v1.ndp_mac_addr, vif->addr, ETH_ALEN); in iwl_mvm_send_proto_offload()
192 common = &cmd.v1.common; in iwl_mvm_send_proto_offload()
193 size = sizeof(cmd.v1); in iwl_mvm_send_proto_offload()
/drivers/gpu/drm/amd/amdkfd/
A Dcwsr_trap_handler_gfx10.asm560 v_mov_b32 v1, 0x0 //Offset[63:32] from buffer resource
716 ds_read_b32 v1, v0
736 ds_read_b32 v1, v0
754 ds_read_b32 v1, v0
774 ds_read_b32 v1, v0
824 v_movrels_b32 v1, v1 //v1 = v[1+m0]
839 v_movrels_b32 v1, v1 //v1 = v[1+m0]
869 v_movrels_b32 v1, v1 //v1 = v[1+m0]
884 v_movrels_b32 v1, v1 //v1 = v[1+m0]
1051 v_movreld_b32 v1, v1
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