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Searched refs:v21 (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_wrapper.c22 if (!((*dml_ctx)->v21.dml_init.dml2_instance)) in dml21_allocate_memory()
25 (*dml_ctx)->v21.mode_support.dml2_instance = (*dml_ctx)->v21.dml_init.dml2_instance; in dml21_allocate_memory()
26 (*dml_ctx)->v21.mode_programming.dml2_instance = (*dml_ctx)->v21.dml_init.dml2_instance; in dml21_allocate_memory()
28 (*dml_ctx)->v21.mode_support.display_config = &(*dml_ctx)->v21.display_config; in dml21_allocate_memory()
29 (*dml_ctx)->v21.mode_programming.display_config = (*dml_ctx)->v21.mode_support.display_config; in dml21_allocate_memory()
32 if (!((*dml_ctx)->v21.mode_programming.programming)) in dml21_allocate_memory()
65 dml2_initialize_instance(&dml_ctx->v21.dml_init); in dml21_init()
83 vfree(dml2->v21.dml_init.dml2_instance); in dml21_destroy()
84 vfree(dml2->v21.mode_programming.programming); in dml21_destroy()
437 dst_dml_ctx->v21.mode_support.display_config = &dst_dml_ctx->v21.display_config; in dml21_copy()
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A Ddml21_utils.c18 …if (ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[i] && ctx->v21.dml_to_dc_pipe_… in dml21_helper_find_dml_pipe_idx_by_stream_id()
29 …if (ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[i] && ctx->v21.dml_to_dc_pipe_m… in dml21_find_dml_pipe_idx_by_plane_id()
106 main_stream_id = dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[dml_stream_index]; in dml21_find_dc_pipes_for_plane()
335 dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[dml_stream_index]); in dml21_handle_phantom_streams_planes()
347 &dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_index]); in dml21_handle_phantom_streams_planes()
365 &dml_ctx->v21.mode_programming.programming->plane_programming[dml_plane_index]); in dml21_handle_phantom_streams_planes()
374 …dml2_map_dc_pipes(dml_ctx, context, NULL, &dml_ctx->v21.dml_to_dc_pipe_mapping, dc->current_state); in dml21_handle_phantom_streams_planes()
390 if (dml_ctx->v21.mode_programming.programming->fams2_required) { in dml21_build_fams2_programming()
416 … &dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_idx].fams2_base_params, in dml21_build_fams2_programming()
425 … &dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_idx].fams2_sub_params, in dml21_build_fams2_programming()
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A Ddml21_translation_helper.c820 struct pipe_ctx *temp_pipe = &dml_ctx->v21.scratch.temp_pipe; in get_scaler_data_for_plane()
1017 …if (dml_ctx->v21.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[i] && dml_ctx->v21.dml_to_dc_p… in map_stream_to_dml21_display_cfg()
1039 …if (dml_ctx->v21.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[i] && dml_ctx->v21.dml_to_dc_pi… in map_plane_to_dml21_display_cfg()
1077 struct dml2_display_cfg *dml_dispcfg = &dml_ctx->v21.display_config; in dml21_map_dc_state_into_dml_display_cfg()
1080 memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping)); in dml21_map_dc_state_into_dml_display_cfg()
1110 dml_ctx->v21.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[disp_cfg_stream_location] = true; in dml21_map_dc_state_into_dml_display_cfg()
1198 const struct dml2_display_cfg_programming *programming = in_ctx->v21.mode_programming.programming; in dml21_extract_watermark_sets()
1218 …dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[i] = dml_ctx->v21.dml_to_dc_pipe_map… in dml21_map_hw_resources()
1219 dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[i] = true; in dml21_map_hw_resources()
1220 …dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[i] = dml_ctx->v21.dml_to_dc_pipe_mapp… in dml21_map_hw_resources()
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/drivers/gpu/drm/nouveau/nvkm/engine/gr/
A Dctxgv100.c139 u8 v21 = (1 << (j + 2)) % gr->tpc_total; in gv100_grctx_generate_rop_mapping() local
142 (v21 << 16) | in gv100_grctx_generate_rop_mapping()
/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_internal_types.h153 } v21; member
A Ddml2_dc_resource_mgmt.c837 mpc_factor = ctx->v21.mode_programming.programming->plane_programming[cfg_idx].num_dpps_required; in get_target_mpc_factor()
889 return ctx->v21.mode_programming.programming->stream_programming[cfg_idx].num_odms_required; in get_target_odm_factor()
1064 …odm_mode_array[i] = ctx->v21.mode_programming.programming->stream_programming[i].num_odms_required; in dml2_map_dc_pipes()
1065 …dpp_per_surface_array[i] = ctx->v21.mode_programming.programming->plane_programming[i].num_dpps_re… in dml2_map_dc_pipes()
/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_atomfirmware.c214 struct atom_integrated_system_info_v2_1 v21; member
360 mem_channel_number = igp_info->v21.umachannelnumber; in amdgpu_atomfirmware_get_vram_info()
363 mem_type = igp_info->v21.memorytype; in amdgpu_atomfirmware_get_vram_info()
/drivers/net/wireless/mediatek/mt76/mt7915/
A Dmac.c567 u32 rcpi, ib_rssi, wb_rssi, v20, v21; in mt7915_mac_fill_rx_vector() local
594 v21 = le32_to_cpu(rxv[21]); in mt7915_mac_fill_rx_vector()
597 (FIELD_GET(MT_CRXV_FOE_HI, v21) << MT_CRXV_FOE_SHIFT); in mt7915_mac_fill_rx_vector()

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