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Searched refs:v3 (Results 1 – 25 of 72) sorted by relevance

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/drivers/pci/controller/
A Dpci-v3-semi.c412 v3_unmap_bus(v3); in v3_pci_read_config()
426 v3_unmap_bus(v3); in v3_pci_write_config()
472 if (v3->map) in v3_irq()
484 v3->map = in v3_integrator_init()
486 if (IS_ERR(v3->map)) { in v3_integrator_init()
548 if (v3->non_pre_mem && in v3_pci_setup_resource()
710 struct v3_pci *v3; in v3_pci_probe() local
723 host->sysdata = v3; in v3_pci_probe()
724 v3->dev = dev; in v3_pci_probe()
739 if (IS_ERR(v3->base)) in v3_pci_probe()
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/drivers/char/mwave/
A Dmwavedd.h89 #define PRINTK_4(f,s,v1,v2,v3) \ argument
91 printk(s,v1,v2,v3); \
94 #define PRINTK_5(f,s,v1,v2,v3,v4) \ argument
96 printk(s,v1,v2,v3,v4); \
99 #define PRINTK_6(f,s,v1,v2,v3,v4,v5) \ argument
101 printk(s,v1,v2,v3,v4,v5); \
118 #define PRINTK_4(f,s,v1,v2,v3) argument
119 #define PRINTK_5(f,s,v1,v2,v3,v4) argument
120 #define PRINTK_6(f,s,v1,v2,v3,v4,v5) argument
121 #define PRINTK_7(f,s,v1,v2,v3,v4,v5,v6) argument
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/drivers/gpu/drm/amd/display/dc/inc/
A Dreg_helper.h76 FN(reg, f3), v3)
82 FN(reg, f3), v3,\
90 FN(reg, f3), v3,\
99 FN(reg, f3), v3,\
109 FN(reg, f3), v3,\
120 FN(reg, f3), v3,\
132 FN(reg, f3), v3, \
145 FN(reg, f3), v3, \
243 FN(reg, f3), v3)
249 FN(reg, f3), v3, \
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A Dbw_fixed.h56 struct bw_fixed v3) in bw_min3() argument
58 return bw_min2(bw_min2(v1, v2), v3); in bw_min3()
63 struct bw_fixed v3) in bw_max3() argument
65 return bw_max2(bw_max2(v1, v2), v3); in bw_max3()
A Ddcn_calc_math.h37 float dcn_bw_max3(float v1, float v2, float v3);
38 float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5);
/drivers/gpu/drm/amd/amdgpu/
A Datombios_crtc.c237 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; member
294 args.v3.ucEnable = enable; in amdgpu_atombios_crtc_program_ss()
405 args.v3.sInput.ucDispPllConfig = 0; in amdgpu_atombios_crtc_adjust_pll()
407 args.v3.sInput.ucDispPllConfig |= in amdgpu_atombios_crtc_adjust_pll()
410 args.v3.sInput.ucDispPllConfig |= in amdgpu_atombios_crtc_adjust_pll()
433 if (args.v3.sOutput.ucRefDiv) { in amdgpu_atombios_crtc_adjust_pll()
438 if (args.v3.sOutput.ucPostDiv) { in amdgpu_atombios_crtc_adjust_pll()
461 PIXEL_CLOCK_PARAMETERS_V3 v3; member
630 args.v3.ucFracFbDiv = frac_fb_div; in amdgpu_atombios_crtc_program_pll()
631 args.v3.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
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A Datombios_encoders.c554 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; member
601 args.v3.ucPanelMode = panel_mode; in amdgpu_atombios_encoder_setup_dig_encoder()
633 args.v3.ucAction = action; in amdgpu_atombios_encoder_setup_dig_encoder()
636 args.v3.ucPanelMode = panel_mode; in amdgpu_atombios_encoder_setup_dig_encoder()
641 args.v3.ucLaneNum = dp_lane_count; in amdgpu_atombios_encoder_setup_dig_encoder()
643 args.v3.ucLaneNum = 8; in amdgpu_atombios_encoder_setup_dig_encoder()
645 args.v3.ucLaneNum = 4; in amdgpu_atombios_encoder_setup_dig_encoder()
904 args.v3.ucAction = action; in amdgpu_atombios_encoder_setup_dig_transmitter()
922 args.v3.ucLaneNum = 8; in amdgpu_atombios_encoder_setup_dig_transmitter()
924 args.v3.ucLaneNum = 4; in amdgpu_atombios_encoder_setup_dig_transmitter()
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A Damdgpu_atombios.c897 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; member
981 if (ss_assign->v3.ucSpreadSpectrumMode & in amdgpu_atombios_get_asic_ss_info()
1045 dividers->post_div = args.v3.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
1052 dividers->ref_div = args.v3.ucRefDiv; in amdgpu_atombios_get_clock_dividers()
1053 dividers->vco_mode = (args.v3.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1218 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; member
1246 args.v3.ucVoltageType = voltage_type; in amdgpu_atombios_get_max_vddc()
1274 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; member
1280 union _ATOM_VOLTAGE_OBJECT_V3 v3; member
1289 u8 *start = (u8 *)v3; in amdgpu_atombios_lookup_voltage_object_v3()
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/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/
A Dlib_float_math.c69 double math_max3(double v1, double v2, double v3) in math_max3() argument
71 return v3 > math_max2(v1, v2) ? v3 : math_max2(v1, v2); in math_max3()
74 double math_max4(double v1, double v2, double v3, double v4) in math_max4() argument
76 return v4 > math_max3(v1, v2, v3) ? v4 : math_max3(v1, v2, v3); in math_max4()
79 double math_max5(double v1, double v2, double v3, double v4, double v5) in math_max5() argument
81 return math_max3(v1, v2, v3) > math_max2(v4, v5) ? math_max3(v1, v2, v3) : math_max2(v4, v5); in math_max5()
A Dlib_float_math.h15 double math_max3(double v1, double v2, double v3);
16 double math_max4(double v1, double v2, double v3, double v4);
17 double math_max5(double v1, double v2, double v3, double v4, double v5);
/drivers/gpu/drm/amd/display/dmub/src/
A Ddmub_reg.h70 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ argument
74 FN(reg, f3), v3)
76 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ argument
80 FN(reg, f3), v3, \
97 #define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3) \ argument
101 FN(reg, f3), v3)
103 #define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ argument
107 FN(reg, f3), v3, \
/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calc_math.c94 float dcn_bw_max3(float v1, float v2, float v3) in dcn_bw_max3() argument
96 return v3 > dcn_bw_max2(v1, v2) ? v3 : dcn_bw_max2(v1, v2); in dcn_bw_max3()
99 float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5) in dcn_bw_max5() argument
101 …return dcn_bw_max3(v1, v2, v3) > dcn_bw_max2(v4, v5) ? dcn_bw_max3(v1, v2, v3) : dcn_bw_max2(v4, v… in dcn_bw_max5()
/drivers/iommu/arm/arm-smmu-v3/
A DMakefile3 arm_smmu_v3-y := arm-smmu-v3.o
4 arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_IOMMUFD) += arm-smmu-v3-iommufd.o
5 arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_SVA) += arm-smmu-v3-sva.o
8 obj-$(CONFIG_ARM_SMMU_V3_KUNIT_TEST) += arm-smmu-v3-test.o
/drivers/clocksource/
A Dacpi_pm.c47 u32 v1 = 0, v2 = 0, v3 = 0; in acpi_pm_read_verified() local
58 v3 = read_pmtmr(); in acpi_pm_read_verified()
59 } while (unlikely((v1 > v2 && v1 < v3) || (v2 > v3 && v2 < v1) in acpi_pm_read_verified()
60 || (v3 > v1 && v3 < v2))); in acpi_pm_read_verified()
/drivers/gpu/drm/radeon/
A Datombios_encoders.c826 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; member
880 args.v3.ucPanelMode = panel_mode; in atombios_dig_encoder_setup2()
914 args.v3.ucAction = action; in atombios_dig_encoder_setup2()
917 args.v3.ucPanelMode = panel_mode; in atombios_dig_encoder_setup2()
922 args.v3.ucLaneNum = dp_lane_count; in atombios_dig_encoder_setup2()
924 args.v3.ucLaneNum = 8; in atombios_dig_encoder_setup2()
926 args.v3.ucLaneNum = 4; in atombios_dig_encoder_setup2()
1177 args.v3.ucAction = action; in atombios_dig_transmitter_setup2()
1195 args.v3.ucLaneNum = 8; in atombios_dig_transmitter_setup2()
1197 args.v3.ucLaneNum = 4; in atombios_dig_transmitter_setup2()
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A Datombios_crtc.c440 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; member
498 args.v3.ucEnable = enable; in atombios_crtc_program_ss()
702 args.v3.sInput.ucDispPllConfig = 0; in atombios_adjust_pll()
704 args.v3.sInput.ucDispPllConfig |= in atombios_adjust_pll()
707 args.v3.sInput.ucDispPllConfig |= in atombios_adjust_pll()
730 if (args.v3.sOutput.ucRefDiv) { in atombios_adjust_pll()
735 if (args.v3.sOutput.ucPostDiv) { in atombios_adjust_pll()
758 PIXEL_CLOCK_PARAMETERS_V3 v3; member
870 args.v3.ucFracFbDiv = frac_fb_div; in atombios_crtc_program_pll()
871 args.v3.ucPostDiv = post_div; in atombios_crtc_program_pll()
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A Dradeon_atombios.c1502 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; member
2888 dividers->post_div = args.v3.ucPostDiv; in radeon_atom_get_clock_dividers()
2895 dividers->ref_div = args.v3.ucRefDiv; in radeon_atom_get_clock_dividers()
3102 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; member
3130 args.v3.ucVoltageType = voltage_type; in radeon_atom_set_voltage()
3165 args.v3.ucVoltageType = voltage_type; in radeon_atom_get_max_vddc()
3201 args.v3.ucVoltageType = 0; in radeon_atom_get_leakage_id_from_vbios()
3203 args.v3.usVoltageLevel = 0; in radeon_atom_get_leakage_id_from_vbios()
3381 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; member
3387 union _ATOM_VOLTAGE_OBJECT_V3 v3; member
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/drivers/gpu/ipu-v3/
A DMakefile2 obj-$(CONFIG_IMX_IPUV3_CORE) += imx-ipu-v3.o
4 imx-ipu-v3-objs := ipu-common.o ipu-cpmem.o ipu-csi.o ipu-dc.o ipu-di.o \
9 imx-ipu-v3-objs += ipu-pre.o ipu-prg.o
/drivers/gpu/drm/amd/amdkfd/
A Dcwsr_trap_handler_gfx10.asm522 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:128*3
545 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:256*3
826 v_movrels_b32 v3, v3 //v3 = v[3+m0]
841 v_movrels_b32 v3, v3 //v3 = v[3+m0]
846 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:128*3
871 v_movrels_b32 v3, v3 //v3 = v[3+m0]
886 v_movrels_b32 v3, v3 //v3 = v[3+m0]
891 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:256*3
1048 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE offset:128*3
1053 v_movreld_b32 v3, v3
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A Dcwsr_trap_handler_gfx8.asm355 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3
396 v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2 // tid
397 v_mul_i32_i24 v2, v3, 8 // tid*8
398 v_mov_b32 v3, 256*2
409 v_add_u32 v2, vcc[0:1], v2, v3
448 v_mov_b32 v3, v3 //v0 = v[0+m0]
453 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3
550 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3
555 v_mov_b32 v3, v3
565 …buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256…
A Dcwsr_trap_handler_gfx12.asm396 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:128*3
406 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:256*3
649 v_movrels_b32 v3, v3 //v3 = v[3+m0]
654 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:128*3
675 v_movrels_b32 v3, v3 //v3 = v[3+m0]
680 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:256*3
815 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS offset:128*3
820 v_movreld_b32 v3, v3
830 …buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS offset:12…
849 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS offset:256*3
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A Dcwsr_trap_handler_gfx9.asm571 v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2 // tid
577 v_lshlrev_b32 v2, 2, v3
602 v_mul_i32_i24 v2, v3, 8 // tid*8
603 v_mov_b32 v3, 256*2
615 v_add_u32 v2, v2, v3
670 v_mov_b32 v3, v3 //v0 = v[0+m0]
816 v_mov_b32 v3, v3
1021 buffer_store_dword v3, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS offset:256*3
1028 buffer_load_dword v3, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS offset:256*3
/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/
A Dfwsec.c67 } v3; member
107 dmemmap->v3.init_cmd = init_cmd; in nvkm_gsp_fwsec_patch()
109 frtscmd = (void *)(dmem + dmemmap->v3.cmd_in_buffer_offset); in nvkm_gsp_fwsec_patch()
168 } v3; member
294 case 3: ret = nvkm_gsp_fwsec_v3(gsp, name, &desc->v3, size, init_cmd, &fw); break; in nvkm_gsp_fwsec()
/drivers/net/wireless/realtek/rtl818x/
A DKconfig17 Belkin F5D6020 v3
18 Belkin F5D6020 v3
78 (v1 = rt73usb; v3 is rt2070-based,
/drivers/net/wireless/intel/iwlwifi/fw/
A Dregulatory.c366 gain = cmd->v3.gain[0]; in iwl_fill_ppag_table()
367 *cmd_size = sizeof(cmd->v3); in iwl_fill_ppag_table()
368 cmd->v3.ppag_config_info.table_source = fwrt->ppag_bios_source; in iwl_fill_ppag_table()
369 cmd->v3.ppag_config_info.table_revision = fwrt->ppag_bios_rev; in iwl_fill_ppag_table()
370 cmd->v3.ppag_config_info.value = cpu_to_le32(fwrt->ppag_flags); in iwl_fill_ppag_table()
404 le32_to_cpu(cmd->v3.ppag_config_info.value)); in iwl_fill_ppag_table()

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