Home
last modified time | relevance | path

Searched refs:v5 (Results 1 – 25 of 37) sorted by relevance

12

/drivers/input/rmi4/
A Drmi_f34.c61 ret = rmi_read(rmi_dev, f34->v5.ctrl_address, &f34->v5.status); in rmi_f34_command()
71 ret = rmi_write(rmi_dev, f34->v5.ctrl_address, f34->v5.status); in rmi_f34_command()
82 ret = rmi_read(rmi_dev, f34->v5.ctrl_address, &f34->v5.status); in rmi_f34_command()
266 if (image_size && image_size != f34->v5.fw_blocks * f34->v5.block_size) { in rmi_f34_update_firmware()
269 image_size, f34->v5.fw_blocks * f34->v5.block_size); in rmi_f34_update_firmware()
274 config_size != f34->v5.config_blocks * f34->v5.block_size) { in rmi_f34_update_firmware()
278 f34->v5.config_blocks * f34->v5.block_size); in rmi_f34_update_firmware()
545 f34->v5.block_size; in rmi_f34v5_probe()
551 f34->v5.block_size); in rmi_f34v5_probe()
553 f34->v5.fw_blocks); in rmi_f34v5_probe()
[all …]
A Drmi_f34.h286 struct f34v5_data v5; member
/drivers/char/mwave/
A Dmwavedd.h99 #define PRINTK_6(f,s,v1,v2,v3,v4,v5) \ argument
101 printk(s,v1,v2,v3,v4,v5); \
104 #define PRINTK_7(f,s,v1,v2,v3,v4,v5,v6) \ argument
106 printk(s,v1,v2,v3,v4,v5,v6); \
109 #define PRINTK_8(f,s,v1,v2,v3,v4,v5,v6,v7) \ argument
111 printk(s,v1,v2,v3,v4,v5,v6,v7); \
120 #define PRINTK_6(f,s,v1,v2,v3,v4,v5) argument
121 #define PRINTK_7(f,s,v1,v2,v3,v4,v5,v6) argument
122 #define PRINTK_8(f,s,v1,v2,v3,v4,v5,v6,v7) argument
/drivers/gpu/drm/amd/display/dc/inc/
A Dreg_helper.h86 f5, v5) \ argument
92 FN(reg, f5), v5)
95 f5, v5, f6, v6) \ argument
101 FN(reg, f5), v5,\
111 FN(reg, f5), v5,\
122 FN(reg, f5), v5,\
134 FN(reg, f5), v5, \
147 FN(reg, f5), v5, \
258 FN(reg, f5), v5)
266 FN(reg, f5), v5, \
[all …]
A Ddcn_calc_math.h38 float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5);
/drivers/gpu/drm/amd/amdgpu/
A Datombios_encoders.c556 DIG_ENCODER_CONTROL_PARAMETERS_V5 v5; member
694 args.v5.asStreamParam.ucDigMode = in amdgpu_atombios_encoder_setup_dig_encoder()
700 args.v5.asStreamParam.ucLaneNum = 8; in amdgpu_atombios_encoder_setup_dig_encoder()
702 args.v5.asStreamParam.ucLaneNum = 4; in amdgpu_atombios_encoder_setup_dig_encoder()
703 args.v5.asStreamParam.ulPixelClock = in amdgpu_atombios_encoder_setup_dig_encoder()
1025 args.v5.ucAction = action; in amdgpu_atombios_encoder_setup_dig_transmitter()
1055 args.v5.ucLaneNum = dp_lane_count; in amdgpu_atombios_encoder_setup_dig_transmitter()
1057 args.v5.ucLaneNum = 8; in amdgpu_atombios_encoder_setup_dig_transmitter()
1059 args.v5.ucLaneNum = 4; in amdgpu_atombios_encoder_setup_dig_transmitter()
1075 args.v5.asConfig.ucHPDSel = 0; in amdgpu_atombios_encoder_setup_dig_transmitter()
[all …]
A Datombios_crtc.c462 PIXEL_CLOCK_PARAMETERS_V5 v5; member
491 args.v5.ucCRTC = ATOM_CRTC_INVALID; in amdgpu_atombios_crtc_set_disp_eng_pll()
492 args.v5.usPixelClock = cpu_to_le16(dispclk); in amdgpu_atombios_crtc_set_disp_eng_pll()
493 args.v5.ucPpll = ATOM_DCPLL; in amdgpu_atombios_crtc_set_disp_eng_pll()
643 args.v5.ucCRTC = crtc_id; in amdgpu_atombios_crtc_program_pll()
645 args.v5.ucRefDiv = ref_div; in amdgpu_atombios_crtc_program_pll()
646 args.v5.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
648 args.v5.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
669 args.v5.ucTransmitterID = encoder_id; in amdgpu_atombios_crtc_program_pll()
670 args.v5.ucEncoderMode = encoder_mode; in amdgpu_atombios_crtc_program_pll()
[all …]
A Damdgpu_atombios.c1011 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; member
1059 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); in amdgpu_atombios_get_clock_dividers()
1061 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN; in amdgpu_atombios_get_clock_dividers()
1067 dividers->post_div = args.v5.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
1068 dividers->enable_post_div = (args.v5.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1070 dividers->enable_dithen = (args.v5.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1072 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv); in amdgpu_atombios_get_clock_dividers()
1073 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac); in amdgpu_atombios_get_clock_dividers()
1074 dividers->ref_div = args.v5.ucRefDiv; in amdgpu_atombios_get_clock_dividers()
1075 dividers->vco_mode = (args.v5.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
A Dgfx_v10_3_0_cleaner_shader.asm65 v_movreld_b32 v5, 0
A Dgfx_v11_0_3_cleaner_shader.asm60 v_movreld_b32 v5, 0
A Dgfx_v10_1_10_cleaner_shader.asm66 v_movreld_b32 v5, 0
A Dgfx_v9_4_3_cleaner_shader.asm71 v_mov_b32 v5, 0
A Dgfx_v9_4_2_cleaner_shader.asm71 v_mov_b32 v5, 0
/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calc_math.c99 float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5) in dcn_bw_max5() argument
101 …return dcn_bw_max3(v1, v2, v3) > dcn_bw_max2(v4, v5) ? dcn_bw_max3(v1, v2, v3) : dcn_bw_max2(v4, v… in dcn_bw_max5()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/
A Dlib_float_math.c79 double math_max5(double v1, double v2, double v3, double v4, double v5) in math_max5() argument
81 return math_max3(v1, v2, v3) > math_max2(v4, v5) ? math_max3(v1, v2, v3) : math_max2(v4, v5); in math_max5()
A Dlib_float_math.h17 double math_max5(double v1, double v2, double v3, double v4, double v5);
/drivers/net/wireless/intel/iwlwifi/mld/
A Dregulatory.c77 .v5.ops = cpu_to_le32(IWL_PER_CHAIN_OFFSET_SET_TABLES), in iwl_mld_geo_sar_init()
78 .v5.table_revision = sk, in iwl_mld_geo_sar_init()
82 ret = iwl_sar_geo_fill_table(&mld->fwrt, &cmd.v5.table[0][0], in iwl_mld_geo_sar_init()
83 ARRAY_SIZE(cmd.v5.table[0]), in iwl_mld_geo_sar_init()
92 return iwl_mld_send_cmd_pdu(mld, cmd_id, &cmd, sizeof(cmd.v5)); in iwl_mld_geo_sar_init()
A Dscan.c899 cfg->v5.iter_count = 1; in iwl_mld_scan_cfg_channels_6g()
900 cfg->v5.iter_interval = 0; in iwl_mld_scan_cfg_channels_6g()
1051 cfg->v5.psd_20 = psd_20; in iwl_mld_scan_cfg_channels_6g()
1137 cfg->v5.iter_count = 1; in iwl_mld_scan_cmd_set_chan_params()
1138 cfg->v5.iter_interval = 0; in iwl_mld_scan_cmd_set_chan_params()
1139 cfg->v5.psd_20 = in iwl_mld_scan_cmd_set_chan_params()
/drivers/gpu/drm/radeon/
A Datombios_encoders.c1298 args.v5.ucAction = action; in atombios_dig_transmitter_setup2()
1307 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; in atombios_dig_transmitter_setup2()
1309 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; in atombios_dig_transmitter_setup2()
1313 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; in atombios_dig_transmitter_setup2()
1324 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; in atombios_dig_transmitter_setup2()
1328 args.v5.ucLaneNum = dp_lane_count; in atombios_dig_transmitter_setup2()
1330 args.v5.ucLaneNum = 8; in atombios_dig_transmitter_setup2()
1332 args.v5.ucLaneNum = 4; in atombios_dig_transmitter_setup2()
1345 args.v5.asConfig.ucCoherentMode = 1; in atombios_dig_transmitter_setup2()
1348 args.v5.asConfig.ucHPDSel = 0; in atombios_dig_transmitter_setup2()
[all …]
A Datombios_crtc.c759 PIXEL_CLOCK_PARAMETERS_V5 v5; member
787 args.v5.ucCRTC = ATOM_CRTC_INVALID; in atombios_crtc_set_disp_eng_pll()
788 args.v5.usPixelClock = cpu_to_le16(dispclk); in atombios_crtc_set_disp_eng_pll()
789 args.v5.ucPpll = ATOM_DCPLL; in atombios_crtc_set_disp_eng_pll()
883 args.v5.ucCRTC = crtc_id; in atombios_crtc_program_pll()
885 args.v5.ucRefDiv = ref_div; in atombios_crtc_program_pll()
886 args.v5.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
888 args.v5.ucPostDiv = post_div; in atombios_crtc_program_pll()
908 args.v5.ucTransmitterID = encoder_id; in atombios_crtc_program_pll()
909 args.v5.ucEncoderMode = encoder_mode; in atombios_crtc_program_pll()
[all …]
/drivers/ufs/host/
A Dufs-mediatek-sip.h50 unsigned long v5; member
60 s.v1, s.v2, s.v3, s.v4, s.v5, s.v6, s.res); in _ufs_mtk_smc()
/drivers/irqchip/
A DMakefile40 obj-$(CONFIG_ARM_GIC_V5) += irq-gic-v5.o irq-gic-v5-irs.o irq-gic-v5-its.o \
41 irq-gic-v5-iwb.o
/drivers/crypto/ccp/
A DMakefile7 ccp-dev-v5.o \
/drivers/net/wireless/intel/iwlwifi/fw/api/
A Dpower.h383 struct iwl_dev_tx_power_cmd_v5 v5; member
532 struct iwl_geo_tx_power_profiles_cmd_v5 v5; member
/drivers/net/wireless/intel/iwlwifi/mvm/
A Dfw.c880 len = sizeof(cmd.v5); in iwl_mvm_sar_select_profile()
882 per_chain = cmd.v5.per_chain[0][0]; in iwl_mvm_sar_select_profile()
935 len = sizeof(geo_tx_cmd.v5); in iwl_mvm_get_sar_geo_profile()
996 len = sizeof(cmd.v5); in iwl_mvm_sar_geo_init()
997 n_bands = ARRAY_SIZE(cmd.v5.table[0]); in iwl_mvm_sar_geo_init()
999 cmd.v5.table_revision = sk; in iwl_mvm_sar_geo_init()

Completed in 76 milliseconds

12