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Searched refs:v_taps (Results 1 – 25 of 27) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/sspl/
A Ddc_spl.c697 spl_scratch->scl_data.taps.v_taps, in spl_calculate_inits_and_viewports()
884 (taps.v_taps == 3 || taps.v_taps == 4 || taps.v_taps == 6)) in spl_get_isharp_en()
907 if (in_taps->v_taps == 0) { in spl_get_taps_non_adaptive_scaler()
912 spl_scratch->scl_data.taps.v_taps = 4; in spl_get_taps_non_adaptive_scaler()
914 spl_scratch->scl_data.taps.v_taps = in_taps->v_taps; in spl_get_taps_non_adaptive_scaler()
958 spl_scratch->scl_data.taps.v_taps = 1; in spl_get_taps_non_adaptive_scaler()
1012 spl_scratch->scl_data.taps.v_taps = 6; in spl_get_optimal_number_of_taps()
1217 dscl_prog_data->taps.v_taps = scl_data->taps.v_taps - 1; in spl_set_taps_data()
1657 if (data->taps.v_taps == 6) in spl_set_isharp_noise_det_mode()
1659 else if (data->taps.v_taps == 4) in spl_set_isharp_noise_det_mode()
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A Ddc_spl_scl_easf_filters.c2368 data->taps.v_taps, data->recip_ratios.vert); in spl_set_filters_data()
2374 data->taps.v_taps, data->ratios.vert); in spl_set_filters_data()
A Ddc_spl_isharp_filters.c551 spl_dscl_get_blur_scale_coeffs_64p(data->taps.v_taps); in spl_set_blur_scale_data()
A Ddc_spl_types.h38 uint32_t v_taps; member
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_transform.c133 SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1); in setup_scaling_configuration()
166 SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1); in dce60_setup_scaling_configuration()
449 data->taps.v_taps, in dce_transform_set_scaler()
454 data->taps.v_taps, in dce_transform_set_scaler()
534 data->taps.v_taps, in dce60_transform_set_scaler()
539 data->taps.v_taps, in dce60_transform_set_scaler()
1182 if (in_taps->v_taps >= max_num_of_lines) in dce_transform_get_optimal_number_of_taps()
1195 scl_data->taps.v_taps = decide_taps(scl_data->ratios.vert, in_taps->v_taps, false); in dce_transform_get_optimal_number_of_taps()
1201 if (in_taps->v_taps == 0 in dce_transform_get_optimal_number_of_taps()
1203 && scl_data->taps.v_taps > 1) { in dce_transform_get_optimal_number_of_taps()
[all …]
/drivers/gpu/drm/amd/display/dc/dpp/dcn201/
A Ddcn201_dpp.c226 if (in_taps->v_taps == 0) { in dpp201_get_optimal_number_of_taps()
228 scl_data->taps.v_taps = 8; in dpp201_get_optimal_number_of_taps()
230 scl_data->taps.v_taps = 4; in dpp201_get_optimal_number_of_taps()
232 scl_data->taps.v_taps = in_taps->v_taps; in dpp201_get_optimal_number_of_taps()
255 scl_data->taps.v_taps = 1; in dpp201_get_optimal_number_of_taps()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
A Ddml_top_display_cfg_types.h230 unsigned int v_taps; member
237 unsigned int v_taps; member
296 unsigned long v_taps; member
/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
A Ddcn10_dpp_dscl.c298 v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3 in dpp1_dscl_set_scl_filter()
300 && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1); in dpp1_dscl_set_scl_filter()
319 scl_data->taps.v_taps, scl_data->ratios.vert); in dpp1_dscl_set_scl_filter()
344 dpp, scl_data->taps.v_taps, in dpp1_dscl_set_scl_filter()
463 int vtaps = scl_data->taps.v_taps; in dpp1_dscl_find_lb_memory_config()
689 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, in dpp1_dscl_set_scaler_manual_scale()
A Ddcn10_dpp.c158 if (in_taps->v_taps == 0) in dpp1_get_optimal_number_of_taps()
159 scl_data->taps.v_taps = 4; in dpp1_get_optimal_number_of_taps()
161 scl_data->taps.v_taps = in_taps->v_taps; in dpp1_get_optimal_number_of_taps()
178 scl_data->taps.v_taps = 1; in dpp1_get_optimal_number_of_taps()
/drivers/gpu/drm/amd/display/dc/
A Ddc_spl_translate.c39 spl_scaling_quality->v_taps = scaling_quality->v_taps; in populate_spltaps_from_taps()
48 scaling_quality->v_taps = spl_scaling_quality->v_taps + 1; in populate_taps_from_spltaps()
A Ddc_hw_types.h712 uint32_t v_taps; member
/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
A Ddcn401_dpp_dscl.c309 scl_data->taps.v_taps, scl_data->ratios.vert); in dpp401_dscl_set_scl_filter()
321 v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3 in dpp401_dscl_set_scl_filter()
323 && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1); in dpp401_dscl_set_scl_filter()
358 dpp, scl_data->taps.v_taps, in dpp401_dscl_set_scl_filter()
479 int vtaps = scl_data->taps.v_taps; in dpp401_dscl_find_lb_memory_config()
1037 dpp, scl_data->taps.v_taps, in dpp401_dscl_program_isharp()
1070 uint32_t v_num_taps = scl_data->taps.v_taps - 1; in dpp401_dscl_set_scaler_manual_scale()
1109 v_num_taps = scl_data->dscl_prog_data.taps.v_taps; in dpp401_dscl_set_scaler_manual_scale()
/drivers/gpu/drm/amd/display/dc/dce110/
A Ddce110_transform_v.c167 set_reg_field_value(value, data->taps.v_taps - 1, in setup_scaling_configuration()
176 if (data->taps.h_taps + data->taps.v_taps > 2) { in setup_scaling_configuration()
559 coeffs_v = get_filter_coeffs_64p(data->taps.v_taps, data->ratios.vert); in dce110_xfmv_set_scaler()
571 data->taps.v_taps, in dce110_xfmv_set_scaler()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_translation_helper.c769 plane->composition.scaler_info.plane0.v_taps = 1; in populate_dml21_dummy_plane_cfg()
771 plane->composition.scaler_info.plane1.v_taps = 0; in populate_dml21_dummy_plane_cfg()
907 if ((scaler_data->taps.h_taps > 1) || (scaler_data->taps.v_taps > 1) || in populate_dml21_plane_config_from_plane_state()
937 if (!scaler_data->taps.v_taps) { in populate_dml21_plane_config_from_plane_state()
938 plane->composition.scaler_info.plane0.v_taps = 1; in populate_dml21_plane_config_from_plane_state()
939 plane->composition.scaler_info.plane1.v_taps = 1; in populate_dml21_plane_config_from_plane_state()
941 plane->composition.scaler_info.plane0.v_taps = scaler_data->taps.v_taps; in populate_dml21_plane_config_from_plane_state()
942 plane->composition.scaler_info.plane1.v_taps = scaler_data->taps.v_taps_c; in populate_dml21_plane_config_from_plane_state()
/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
A Ddcn30_dpp.c440 if (in_taps->v_taps == 0) { in dpp3_get_optimal_number_of_taps()
442 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8); in dpp3_get_optimal_number_of_taps()
444 scl_data->taps.v_taps = 4; in dpp3_get_optimal_number_of_taps()
446 scl_data->taps.v_taps = in_taps->v_taps; in dpp3_get_optimal_number_of_taps()
500 if (scl_data->taps.v_taps > max_taps_y) in dpp3_get_optimal_number_of_taps()
501 scl_data->taps.v_taps = max_taps_y; in dpp3_get_optimal_number_of_taps()
510 scl_data->taps.v_taps = 1; in dpp3_get_optimal_number_of_taps()
/drivers/gpu/drm/amd/display/dc/basics/
A Ddce_calcs.c382 data->v_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1); in calculate_bandwidth()
383 data->v_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1); in calculate_bandwidth()
435 data->v_taps[i] = bw_int_to_fixed(1); in calculate_bandwidth()
544 if (bw_mtn(data->vsr[i], data->v_taps[i])) { in calculate_bandwidth()
580 if (bw_mtn(bw_add(data->v_taps[i], bw_int_to_fixed(1)), data->lb_partitions[i])) { in calculate_bandwidth()
1701 …data->scaler_limits_factor = bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_div(da… in calculate_bandwidth()
2829 data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps); in populate_initial_data()
2885 …data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.… in populate_initial_data()
2932 data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps); in populate_initial_data()
2984 …data->v_taps[num_displays + 4] = pipe[i].stream->src.height == pipe[i].stream->dst.height ? bw_int… in populate_initial_data()
[all …]
A Dcalcs_logger.h431 DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_taps[%d]:%d", i, bw_fixed_to_int(data->v_taps[i])); in print_bw_calcs_data()
/drivers/gpu/drm/amd/display/dc/core/
A Ddc_debug.c167 update->scaling_info->scaling_quality.v_taps, in update_surface_trace()
A Ddc_resource.c1317 data->taps.v_taps, in calculate_inits_and_viewports()
1574 if (res && (pipe_ctx->plane_res.scl_data.taps.v_taps != temp.v_taps || in resource_build_scaling_params()
/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_dwb_scl.c807 uint32_t v_taps_luma = num_taps.v_taps; in dwb_program_vert_scalar()
/drivers/gpu/drm/amd/display/dc/inc/
A Ddce_calcs.h397 struct bw_fixed v_taps[maximum_number_of_surfaces]; member
/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_translation_helper.c1112 if (!scaler_data->taps.v_taps) { in populate_dml_plane_cfg_from_plane_state()
1116 out->VTaps[location] = scaler_data->taps.v_taps; in populate_dml_plane_cfg_from_plane_state()
1249 out->WritebackVTaps[location] = wb_info->dwb_params.scaler_taps.v_taps > 0 ? in populate_dml_writeback_cfg_from_stream_state()
1250 wb_info->dwb_params.scaler_taps.v_taps : 1; in populate_dml_writeback_cfg_from_stream_state()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
A Ddml2_core_dcn4_calcs.c6769 double v_taps = p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport() local
6783 DML_LOG_VERBOSE("DML::%s: k=%u, VTaps = %f\n", __func__, k, v_taps); in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
7413 myPipe->VTaps = display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps; in dml_core_ms_prefetch_check()
8003 || display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps != 1.0)) { in dml_core_mode_support()
8005 …].composition.scaler_info.plane0.v_taps < 1.0 || display_cfg->plane_descriptors[k].composition.sca… in dml_core_mode_support()
8013 …k].composition.scaler_info.plane1.v_taps < 1 || display_cfg->plane_descriptors[k].composition.scal… in dml_core_mode_support()
8144 display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps, in dml_core_mode_support()
8145 display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps, in dml_core_mode_support()
10492 display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps, in dml_core_mode_programming()
10493 display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps, in dml_core_mode_programming()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calcs.c404 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps; in pipe_ctx_to_e2e_pipe_params()
1013 v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps; in dcn_validate_bandwidth()
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddcn30_fpu.c220 dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps; in dcn30_fpu_populate_dml_writeback_from_context()

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