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/drivers/gpu/drm/amd/display/modules/freesync/
A Dfreesync.c140 unsigned int v_total; in mod_freesync_calc_v_total_from_refresh() local
173 if (v_total < stream->timing.v_total) { in mod_freesync_calc_v_total_from_refresh()
174 ASSERT(v_total < stream->timing.v_total); in mod_freesync_calc_v_total_from_refresh()
175 v_total = stream->timing.v_total; in mod_freesync_calc_v_total_from_refresh()
178 return v_total; in mod_freesync_calc_v_total_from_refresh()
208 if (v_total < stream->timing.v_total) { in calc_v_total_from_duration()
209 ASSERT(v_total < stream->timing.v_total); in calc_v_total_from_duration()
210 v_total = stream->timing.v_total; in calc_v_total_from_duration()
213 return v_total; in calc_v_total_from_duration()
283 if (v_total < stream->timing.v_total) in update_v_total_for_static_ramp()
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/drivers/video/fbdev/matrox/
A Dmatroxfb_g450.c236 unsigned int v_total; member
341 if (vtotal < outd->v_total) { in computeRegs()
346 vdisplay = outd->v_total - 4; in computeRegs()
347 vsyncend = outd->v_total; in computeRegs()
350 r->regs[0x17] = outd->v_total / 4; in computeRegs()
351 r->regs[0x18] = outd->v_total & 3; in computeRegs()
357 mt->VSyncStart = outd->v_total - 2; in computeRegs()
358 mt->VSyncEnd = outd->v_total; in computeRegs()
359 mt->VTotal = outd->v_total; in computeRegs()
371 .v_total = 625, in cve2_init_TVdata()
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/drivers/gpu/ipu-v3/
A Dipu-di.c207 u32 v_total = sig->mode.vactive + sig->mode.vsync_len + in ipu_di_sync_config_interlaced() local
212 .run_count = v_total * 2 - 1, in ipu_di_sync_config_interlaced()
223 .run_count = v_total - 1, in ipu_di_sync_config_interlaced()
231 .run_count = v_total / 2, in ipu_di_sync_config_interlaced()
262 ipu_di_write(di, v_total / 2 - 1, DI_SCR_CONF); in ipu_di_sync_config_interlaced()
270 u32 v_total = sig->mode.vactive + sig->mode.vsync_len + in ipu_di_sync_config_noninterlaced() local
288 .run_count = v_total - 1, in ipu_di_sync_config_noninterlaced()
323 .run_count = v_total - 1, in ipu_di_sync_config_noninterlaced()
352 .run_count = v_total - 1, in ipu_di_sync_config_noninterlaced()
370 .run_count = v_total - 1, in ipu_di_sync_config_noninterlaced()
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/drivers/gpu/drm/amd/display/dc/optc/dcn10/
A Ddcn10_optc.c170 uint32_t v_total; in optc1_program_timing() local
221 v_total = patched_crtc_timing.v_total - 1; in optc1_program_timing()
224 OTG_V_TOTAL, v_total); in optc1_program_timing()
229 optc->funcs->set_vtotal_min_max(optc, v_total, v_total); in optc1_program_timing()
239 asic_blank_start = patched_crtc_timing.v_total - in optc1_program_timing()
601 v_blank = (timing->v_total - timing->v_addressable - in optc1_validate_timing()
626 timing->v_total > optc1->max_v_total) in optc1_validate_timing()
1322 hw_crtc_timing->v_total = s.v_total + 1; in optc1_get_hw_timing()
1323 hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end); in optc1_get_hw_timing()
1324 hw_crtc_timing->v_front_porch = s.v_total + 1 - s.v_blank_start; in optc1_get_hw_timing()
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/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_mall_phantom.c247 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1) in assign_subvp_pipe()
248 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total); in assign_subvp_pipe()
266 unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total / in assign_subvp_pipe()
377 microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) + in subvp_subvp_schedulable()
464 prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / in dml2_svp_drr_schedulable()
469 drr_frame_us = drr_timing->v_total * drr_timing->h_total / in dml2_svp_drr_schedulable()
475 drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total / in dml2_svp_drr_schedulable()
562 …prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / in subvp_vblank_schedulable()
568 vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total / in subvp_vblank_schedulable()
570 …vblank_blank_us = (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_tota… in subvp_vblank_schedulable()
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/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource_helpers.c452 curr_v_blank = timing->v_total - timing->v_addressable; in get_frame_rate_at_max_stretch_100hz()
454 stretched_frame_pix_cnt = (v_stretch_max + timing->v_total) * timing->h_total; in get_frame_rate_at_max_stretch_100hz()
498 h_v_total = timing->h_total * timing->v_total; in get_refresh_rate()
666 pipe->stream->timing.v_total * (unsigned long long)pipe->stream->timing.h_total - (uint64_t)1); in dcn32_subvp_drr_admissable()
667 refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total); in dcn32_subvp_drr_admissable()
727 pipe->stream->timing.v_total * (unsigned long long)pipe->stream->timing.h_total - (uint64_t)1); in dcn32_subvp_vblank_admissable()
728 refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total); in dcn32_subvp_vblank_admissable()
/drivers/gpu/drm/amd/display/modules/info_packet/
A Dinfo_packet.c467 && stream->timing.v_total >= 2160 in mod_build_hf_vsif_infopacket()
572 info_packet->sb[1] = (stream->timing.v_total & 0x00FF); in mod_build_adaptive_sync_infopacket_v2()
573 info_packet->sb[2] = (stream->timing.v_total & 0xFF00) >> 8; in mod_build_adaptive_sync_infopacket_v2()
/drivers/gpu/drm/amd/display/dc/core/
A Ddc_stream.c835 stream->timing.v_total, in dc_stream_log()
1057 …return (int)div64_s64((long long)stream->timing.pix_clk_100hz*100, stream->timing.v_total*(long lo… in dc_stream_calculate_flickerless_refresh_rate()
1103 if (stream->timing.v_total * stream->timing.h_total == 0) in dc_stream_get_max_flickerless_instant_vtotal_delta()
1106 …nt)div64_s64((long long)stream->timing.pix_clk_100hz*100, stream->timing.v_total*(long long)stream… in dc_stream_get_max_flickerless_instant_vtotal_delta()
1117 …return (((int) stream->timing.v_total - safe_refresh_v_total) >= 0) ? (stream->timing.v_total - sa… in dc_stream_get_max_flickerless_instant_vtotal_delta()
1119 …(safe_refresh_v_total - (int) stream->timing.v_total) >= 0) ? (safe_refresh_v_total - stream->timi… in dc_stream_get_max_flickerless_instant_vtotal_delta()
/drivers/gpu/drm/bridge/
A Dlontium-lt9611.c133 u32 v_total, vactive, vsync_len, vfront_porch, vsync_porch; in lt9611_mipi_video_setup() local
136 v_total = mode->vtotal; in lt9611_mipi_video_setup()
148 regmap_write(lt9611->regmap, 0x830d, (u8)(v_total / 256)); in lt9611_mipi_video_setup()
149 regmap_write(lt9611->regmap, 0x830e, (u8)(v_total % 256)); in lt9611_mipi_video_setup()
291 u32 v_total, vactive, hactive_a, hactive_b, h_total_sysclk; in lt9611_video_check() local
306 v_total = temp; in lt9611_video_check()
328 hactive_a, hactive_b, vactive, v_total, h_total_sysclk); in lt9611_video_check()
A Dlontium-lt8912b.c287 u32 vactive, v_total, vpw, vfp, vbp; in lt8912_video_setup() local
305 v_total = vactive + vfp + vpw + vbp; in lt8912_video_setup()
325 ret |= regmap_write(lt->regmap[I2C_CEC_DSI], 0x36, v_total & 0xff); in lt8912_video_setup()
326 ret |= regmap_write(lt->regmap[I2C_CEC_DSI], 0x37, v_total >> 8); in lt8912_video_setup()
A Dlontium-lt9611uxc.c308 u32 v_total, vactive, vsync_len, vfront_porch; in lt9611uxc_video_setup() local
311 v_total = mode->vtotal; in lt9611uxc_video_setup()
321 regmap_write(lt9611uxc->regmap, 0xd00d, (u8)(v_total / 256)); in lt9611uxc_video_setup()
322 regmap_write(lt9611uxc->regmap, 0xd00e, (u8)(v_total % 256)); in lt9611uxc_video_setup()
/drivers/gpu/drm/radeon/
A Dradeon_legacy_tv.c428 unsigned int h_total, v_total, f_total; in radeon_legacy_tv_init_restarts() local
439 v_total = const_ptr->ver_total; in radeon_legacy_tv_init_restarts()
485 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME); in radeon_legacy_tv_init_restarts()
487 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME); in radeon_legacy_tv_init_restarts()
496 tv_dac->tv.vrestart = restart % v_total; in radeon_legacy_tv_init_restarts()
497 restart /= v_total; in radeon_legacy_tv_init_restarts()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
A Ddce110_clk_mgr.c101 uint32_t vertical_total_min = stream->timing.v_total; in dce110_get_min_vblank_time_us()
165 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) in dce110_fill_display_configs()
166 / stream->timing.v_total; in dce110_fill_display_configs()
/drivers/video/fbdev/aty/
A Daty128fb.c415 u32 v_total, v_sync_strt_wid; member
1020 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total); in aty128_set_crtc()
1037 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; in aty128_var_to_crtc() local
1099 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL; in aty128_var_to_crtc()
1102 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) { in aty128_var_to_crtc()
1131 crtc->v_total = v_total | (v_disp << 16); in aty128_var_to_crtc()
1236 v_total = crtc->v_total & 0x7ff; in aty128_crtc_to_var()
1237 v_disp = (crtc->v_total >> 16) & 0x7ff; in aty128_crtc_to_var()
1250 upper = v_total - v_sync_strt - v_sync_wid; in aty128_crtc_to_var()
1540 ((par->crtc.v_total>>16) & 0x7ff)+1, in aty128fb_set_par()
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/drivers/video/fbdev/nvidia/
A Dnvidia.c310 int v_total = (info->var.yres + info->var.lower_margin + in nvidia_calc_regs() local
313 int v_blank_e = v_total + 1; in nvidia_calc_regs()
320 v_total |= 1; in nvidia_calc_regs()
323 v_start = v_total - 3; in nvidia_calc_regs()
324 v_end = v_total - 2; in nvidia_calc_regs()
339 state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0); in nvidia_calc_regs()
340 state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0) in nvidia_calc_regs()
345 | SetBitField(v_total, 9: 9, 5:5) in nvidia_calc_regs()
368 | SetBitField(v_total, 10: 10, 0:0); in nvidia_calc_regs()
375 state->extra = SetBitField(v_total, 11: 11, 0:0) in nvidia_calc_regs()
/drivers/gpu/drm/amd/display/dc/optc/dcn201/
A Ddcn201_optc.c79 v_blank = (timing->v_total - timing->v_addressable - in optc201_validate_timing()
100 timing->v_total > optc1->max_v_total) in optc201_validate_timing()
/drivers/gpu/drm/amd/display/dc/dce120/
A Ddce120_timing_generator.c108 (timing->v_total - timing->v_addressable - in dce120_timing_generator_validate_timing()
451 timing->v_total - 1); in dce120_timing_generator_program_blanking()
459 timing->v_total - 1); in dce120_timing_generator_program_blanking()
464 timing->v_total - 1); in dce120_timing_generator_program_blanking()
476 tmp1 = timing->v_total - (v_sync_start + timing->v_border_top); in dce120_timing_generator_program_blanking()
628 timing->v_total - timing->v_addressable - in dce120_timing_generator_enable_advanced_request()
/drivers/gpu/drm/amd/display/dc/dml/dcn351/
A Ddcn351_fpu.c464 v_blank = timing->v_total - v_active; in get_vertical_back_porch()
500 pipe->stream->adjust.v_total_min > timing->v_total) { in dcn351_populate_dml_pipes_from_context_fpu()
503 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - in dcn351_populate_dml_pipes_from_context_fpu()
507 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; in dcn351_populate_dml_pipes_from_context_fpu()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
A Ddml2_core_utils.c579 phantom->timing.v_total = meta->v_total; in create_phantom_stream_from_main_stream()
582 …phantom->timing.v_blank_end = phantom->timing.v_total - phantom->timing.v_front_porch - phantom->t… in create_phantom_stream_from_main_stream()
583 phantom->timing.vblank_nom = phantom->timing.v_total - phantom->timing.v_active; in create_phantom_stream_from_main_stream()
/drivers/gpu/drm/amd/display/dc/dml/dcn35/
A Ddcn35_fpu.c431 v_blank = timing->v_total - v_active; in get_vertical_back_porch()
467 pipe->stream->adjust.v_total_min > timing->v_total) { in dcn35_populate_dml_pipes_from_context_fpu()
470 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - in dcn35_populate_dml_pipes_from_context_fpu()
474 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; in dcn35_populate_dml_pipes_from_context_fpu()
/drivers/gpu/drm/amd/display/dc/dml/dcn314/
A Ddcn314_fpu.c301 v_blank = timing->v_total - v_active; in get_vertical_back_porch()
336 pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total; in dcn314_populate_dml_pipes_from_context_fpu()
340 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; in dcn314_populate_dml_pipes_from_context_fpu()
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_mem_input.c692 uint32_t v_total, in get_dmif_switch_time_us() argument
704 if (!h_total || v_total || !pix_clk_khz) in get_dmif_switch_time_us()
709 pixels_per_frame = h_total * v_total; in get_dmif_switch_time_us()
739 uint32_t v_total, in dce_mi_allocate_dmif() argument
747 v_total, in dce_mi_allocate_dmif()
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c541 phantom_stream->timing.v_total = phantom_stream->timing.v_addressable + in dcn32_set_phantom_stream_timing()
619 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1) in dcn32_assign_subvp_pipe()
620 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total); in dcn32_assign_subvp_pipe()
647 unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total / in dcn32_assign_subvp_pipe()
860 drr_frame_us = drr_timing->v_total * drr_timing->h_total / in subvp_drr_schedulable()
956 vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total / in subvp_vblank_schedulable()
1004 refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total); in subvp_subvp_admissable()
1631 asic_blank_start = patched_crtc_timing.v_total - in dcn20_adjust_freesync_v_startup()
3405 refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total); in dcn32_allow_subvp_with_active_margin()
3452 pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total - 1) in dcn32_allow_subvp_high_refresh_rate()
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/drivers/gpu/drm/amd/display/dc/opp/dcn10/
A Ddcn10_opp.c331 uint32_t space1_size = timing->v_total - timing->v_addressable; in opp1_program_stereo()
333 uint32_t space2_size = timing->v_total - timing->v_addressable; in opp1_program_stereo()
/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
A Ddcn10_hwseq.c150 vupdate_end += stream->timing.v_total; in dcn10_wait_for_pipe_update_if_needed()
635 s.v_total, in dcn10_log_hw_state()
2189 vupdate_end += stream->timing.v_total; in delay_cursor_until_vupdate()
2323 pipe->stream->timing.v_total; in is_low_refresh_rate()
2398 hw_crtc_timing[i].v_total; in dcn10_align_pixel_clocks()
3919 asic_blank_end = (patched_crtc_timing.v_total - in dcn10_get_vupdate_offset_from_vsync()
3938 *start_line = vupdate_pos - ((vupdate_pos / timing->v_total) * timing->v_total); in dcn10_calc_vupdate_position()
3940 *start_line = vupdate_pos + ((-vupdate_pos / timing->v_total) + 1) * timing->v_total - 1; in dcn10_calc_vupdate_position()
3941 *end_line = (*start_line + 2) % timing->v_total; in dcn10_calc_vupdate_position()
3961 *start_line = vline_pos - ((vline_pos / timing->v_total) * timing->v_total); in dcn10_cal_vline_position()
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