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Searched refs:val (Results 1 – 25 of 4940) sorted by relevance

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/drivers/media/tuners/
A Dtda18271-maps.c19 u8 val; member
318 { .rfmax = 41000, .val = 0x1e },
319 { .rfmax = 43000, .val = 0x30 },
780 { .rfmax = 30000, .val = 4 },
781 { .rfmax = 200000, .val = 5 },
782 { .rfmax = 600000, .val = 6 },
783 { .rfmax = 865000, .val = 7 },
924 int val, i = 0; in tda18271_lookup_thermometer() local
939 return val; in tda18271_lookup_thermometer()
1104 u32 *freq, u8 *val) in tda18271_lookup_map() argument
[all …]
/drivers/hwtracing/coresight/
A Dcoresight-etm-cp14.c19 *val = etm_read(ETMCR); in etm_readl_cp14()
22 *val = etm_read(ETMCCR); in etm_readl_cp14()
28 *val = etm_read(ETMSR); in etm_readl_cp14()
31 *val = etm_read(ETMSCR); in etm_readl_cp14()
34 *val = etm_read(ETMTSSCR); in etm_readl_cp14()
37 *val = etm_read(ETMTEEVR); in etm_readl_cp14()
40 *val = etm_read(ETMTECR1); in etm_readl_cp14()
43 *val = etm_read(ETMFFLR); in etm_readl_cp14()
46 *val = etm_read(ETMACVR0); in etm_readl_cp14()
49 *val = etm_read(ETMACVR1); in etm_readl_cp14()
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A Dcoresight-etm4x.h262 CASE_##op((val), TRCRSR) \
270 CASE_##op((val), TRCOSLAR)
308 CASE_##op((val), TRCIDR8) \
309 CASE_##op((val), TRCIDR9) \
322 CASE_##op((val), TRCIDR0) \
441 CASE_##op((val), TRCDEVID)
450 CASE_##op((val), TRCLAR) \
451 CASE_##op((val), TRCLSR) \
457 CASE_##op((val), TRCPIDR3)
600 #define ETM_MODE_COND(val) BMVAL(val, 8, 10) argument
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/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
A Dtypes.h174 (NCONF_HAS(val) && (NCONF_IS(val) || ((var) == (val))))
177 (NCONF_GE(val) && (!NCONF_LT(val) || ((var) >= (val))))
180 (NCONF_GT(val) && (!NCONF_LE(val) || ((var) > (val))))
183 (NCONF_LT(val) && (!NCONF_GE(val) || ((var) < (val))))
186 (NCONF_LE(val) && (!NCONF_GT(val) || ((var) <= (val))))
189 (LCNCONF_HAS(val) && (LCNCONF_IS(val) || ((var) == (val))))
192 (LCNCONF_GE(val) && (!LCNCONF_LT(val) || ((var) >= (val))))
195 (LCNCONF_GT(val) && (!LCNCONF_LE(val) || ((var) > (val))))
198 (LCNCONF_LT(val) && (!LCNCONF_GE(val) || ((var) < (val))))
210 (D11CONF_GT(val) && (!D11CONF_LE(val) || ((var) > (val))))
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/drivers/phy/
A Dphy-xgene.c785 val = CMU_REG1_PLL_CP_SET(val, 0x1); in xgene_phy_sata_cfg_cmu_core()
843 val = CMU_REG5_PLL_LFCAP_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
926 val = CMU_REG36_PLL_SSC_EN_SET(val, 1); in xgene_phy_ssc_enable()
959 val = RXTX_REG1_CTLE_EQ_SET(val, in xgene_phy_sata_cfg_lanes()
987 val = RXTX_REG5_TX_CN1_SET(val, in xgene_phy_sata_cfg_lanes()
990 val = RXTX_REG5_TX_CP1_SET(val, in xgene_phy_sata_cfg_lanes()
993 val = RXTX_REG5_TX_CN2_SET(val, in xgene_phy_sata_cfg_lanes()
1000 val = RXTX_REG6_TXAMP_CNTL_SET(val, in xgene_phy_sata_cfg_lanes()
1095 val = RXTX_REG125_SIGN_PQ_SET(val, in xgene_phy_sata_cfg_lanes()
1098 val = RXTX_REG125_PQ_REG_SET(val, in xgene_phy_sata_cfg_lanes()
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/drivers/accel/ivpu/
A Divpu_hw_ip.c73 u32 val = 0; in host_ss_rst_clr() local
75 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, TOP_NOC, val); in host_ss_rst_clr()
76 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, DSS_MAS, val); in host_ss_rst_clr()
77 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, MSS_MAS, val); in host_ss_rst_clr()
245 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val); in idle_gen_drive_40xx()
247 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val); in idle_gen_drive_40xx()
271 u32 val; in pwr_island_delay_set_50xx() local
814 u32 val; in soc_cpu_boot_37xx() local
898 u32 val; in soc_cpu_boot_40xx() local
931 u32 val; in wdt_disable_37xx() local
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/drivers/net/phy/
A Dphy-c45.c20 int val; in genphy_c45_baset1_able() local
24 if (val < 0) in genphy_c45_baset1_able()
400 int val; in genphy_c45_aneg_done() local
407 return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0; in genphy_c45_aneg_done()
477 int val; in genphy_c45_baset1_read_lpa() local
525 int val; in genphy_c45_read_lpa() local
575 int val; in genphy_c45_pma_baset1_read_master_slave() local
1377 val = (val & ~MDIO_OATC14_PLCA_NCNT) | in genphy_c45_plca_set_cfg()
1381 val = (val & ~MDIO_OATC14_PLCA_ID) | in genphy_c45_plca_set_cfg()
1417 val = (val & ~MDIO_OATC14_PLCA_MAXBC) | in genphy_c45_plca_set_cfg()
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/drivers/net/wireless/ath/ath5k/
A Deeprom.c43 u16 val; in ath5k_eeprom_bin2freq() local
61 return val; in ath5k_eeprom_bin2freq()
76 u16 val; in ath5k_eeprom_init_header() local
97 if (val) { in ath5k_eeprom_init_header()
194 u16 val; in ath5k_eeprom_read_ants() local
254 u16 val; in ath5k_eeprom_read_modes() local
517 u16 val; in ath5k_eeprom_read_freq_list() local
553 u16 val; in ath5k_eeprom_init_11a_pcal_freq() local
802 u16 val; in ath5k_eeprom_read_pcal_info_5111() local
1027 u16 val; in ath5k_eeprom_read_pcal_info_5112() local
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/drivers/net/ethernet/chelsio/cxgb4/
A Dcxgb4_tc_u32_parse.h48 f->val.tos = (ntohl(val) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_tos()
88 memcpy(&f->val.fip[0], &val, sizeof(u32)); in cxgb4_fill_ipv4_src_ip()
97 memcpy(&f->val.lip[0], &val, sizeof(u32)); in cxgb4_fill_ipv4_dst_ip()
134 memcpy(&f->val.fip[0], &val, sizeof(u32)); in cxgb4_fill_ipv6_src_ip0()
143 memcpy(&f->val.fip[4], &val, sizeof(u32)); in cxgb4_fill_ipv6_src_ip1()
152 memcpy(&f->val.fip[8], &val, sizeof(u32)); in cxgb4_fill_ipv6_src_ip2()
170 memcpy(&f->val.lip[0], &val, sizeof(u32)); in cxgb4_fill_ipv6_dst_ip0()
179 memcpy(&f->val.lip[4], &val, sizeof(u32)); in cxgb4_fill_ipv6_dst_ip1()
188 memcpy(&f->val.lip[8], &val, sizeof(u32)); in cxgb4_fill_ipv6_dst_ip2()
221 f->val.fport = ntohl(val) >> 16; in cxgb4_fill_l4_ports()
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/drivers/gpu/drm/mcde/
A Dmcde_dsi.c70 u32 val; in mcde_dsi_irq() local
78 if (val) in mcde_dsi_irq()
94 if (val) in mcde_dsi_irq()
111 if (val) in mcde_dsi_irq()
116 if (val) in mcde_dsi_irq()
121 if (val) in mcde_dsi_irq()
219 u32 val; in mcde_dsi_execute_transfer() local
263 val); in mcde_dsi_execute_transfer()
302 u32 val; in mcde_dsi_host_transfer() local
393 u32 val; in mcde_dsi_te_request() local
[all …]
A Dmcde_display.c93 u32 val; in mcde_display_irq() local
199 u32 val; in mcde_configure_extsrc() local
344 u32 val; in mcde_configure_overlay() local
494 u32 val; in mcde_configure_channel() local
634 u32 val; in mcde_configure_fifo() local
753 u32 val; in mcde_configure_dsi_formatter() local
846 u32 val; in mcde_enable_fifo() local
874 u32 val; in mcde_disable_fifo() local
918 u32 val; in mcde_drain_pipe() local
979 u32 val; in mcde_setup_dpi() local
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/drivers/memory/
A Drenesas-xspi-if-regs.h20 #define XSPI_BMCFG_MWRSIZE(val) (((val) & 0xff) << 8) argument
25 #define XSPI_CMCFG0_FFMT(val) (((val) & 0x03) << 0) argument
26 #define XSPI_CMCFG0_ADDSIZE(val) (((val) & 0x03) << 2) argument
30 #define XSPI_CMCFG1_RDCMD(val) (((val) & 0xffff) << 0) argument
32 #define XSPI_CMCFG1_RDLATE(val) (((val) & 0x1f) << 16) argument
36 #define XSPI_CMCFG2_WRCMD(val) (((val) & 0xffff) << 0) argument
38 #define XSPI_CMCFG2_WRLATE(val) (((val) & 0x1f) << 16) argument
42 #define XSPI_LIOCFG_PRTMD(val) (((val) & 0x3ff) << 0) argument
43 #define XSPI_LIOCFG_CSMIN(val) (((val) & 0x0f) << 16) argument
49 #define XSPI_BMCTL0_CS0ACC(val) (((val) & 0x03) << 0) argument
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/drivers/media/platform/qcom/camss/
A Dcamss-csid-gen2.c178 int val; in __csid_configure_rx() local
197 int val; in __csid_ctrl_rdi() local
214 u32 val; in __csid_configure_testgen() local
263 u32 val; in __csid_configure_rdi_stream() local
293 val = 1; in __csid_configure_rdi_stream()
296 val = 0; in __csid_configure_rdi_stream()
299 val = 1; in __csid_configure_rdi_stream()
302 val = 0; in __csid_configure_rdi_stream()
305 val = 1; in __csid_configure_rdi_stream()
308 val = 0; in __csid_configure_rdi_stream()
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/drivers/usb/phy/
A Dphy-tegra-usb.c224 u32 val; in set_pts() local
243 u32 val; in set_phcd() local
330 u32 val; in utmip_pad_power_on() local
370 u32 val; in utmip_pad_power_off() local
420 u32 val; in utmi_phy_clk_disable() local
452 u32 val; in utmi_phy_clk_enable() local
487 u32 val; in utmi_phy_power_on() local
652 u32 val; in utmi_phy_power_off() local
660 val, !(val & VBUS_WAKEUP_STS), in utmi_phy_power_off()
717 u32 val; in ulpi_phy_power_on() local
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/drivers/phy/marvell/
A Dphy-mvebu-cp110-comphy.c340 u32 val; in mvebu_comphy_ethernet_init_reset() local
456 u32 val; in mvebu_comphy_init_plls() local
467 val, in mvebu_comphy_init_plls()
482 val, val & MVEBU_COMPHY_SERDES_STATUS0_RX_INIT, in mvebu_comphy_init_plls()
498 u32 val; in mvebu_comphy_set_mode_sgmii() local
531 u32 val; in mvebu_comphy_set_mode_rxaui() local
584 u32 val; in mvebu_comphy_set_mode_10gbaser() local
727 u32 val; in mvebu_comphy_power_on_legacy() local
878 u32 val; in mvebu_comphy_power_off_legacy() local
1039 u32 val; in mvebu_comphy_probe() local
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/drivers/gpu/drm/i915/display/
A Dintel_fixed.h15 u32 val; member
22 return val.val == 0; in is_fixed16_zero()
27 uint_fixed_16_16_t fp = { .val = val << 16 }; in u32_to_fixed16()
47 uint_fixed_16_16_t min = { .val = min(min1.val, min2.val) }; in min_fixed16()
55 uint_fixed_16_16_t max = { .val = max(max1.val, max2.val) }; in max_fixed16()
72 return DIV_ROUND_UP(val.val, d.val); in div_round_up_fixed16()
79 tmp = mul_u32_u32(val, mul.val); in mul_round_up_u32_fixed16()
91 tmp = mul_u32_u32(val.val, mul.val); in mul_fixed16()
122 tmp = mul_u32_u32(val, mul.val); in mul_u32_fixed16()
132 tmp = (u64)add1.val + add2.val; in add_fixed16()
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/drivers/hwmon/
A Dhwmon-vid.c81 val &= 0x3f; in vid_from_reg()
84 if ((val & 0x1f) <= 0x09 || val == 0x0a) in vid_from_reg()
94 val &= 0xff; in vid_from_reg()
95 if (val < 0x02 || val > 0xb2) in vid_from_reg()
100 val &= 0x1f; in vid_from_reg()
105 val &= 0x3f; in vid_from_reg()
106 return (val < 32) ? 1550 - 25 * val in vid_from_reg()
110 val &= 0x7f; in vid_from_reg()
133 val & 0x10 ? 5100 - (val) * 100 : in vid_from_reg()
137 return val & 0x10 ? 975 - (val & 0xF) * 25 : in vid_from_reg()
[all …]
/drivers/gpu/drm/sprd/
A Dmegacores_pll.c131 regmap_write(regmap, 0x31, val[CLK]); in dphy_set_timing_reg()
137 regmap_write(regmap, 0x90, val[CLK]); in dphy_set_timing_reg()
144 regmap_write(regmap, 0x32, val[CLK]); in dphy_set_timing_reg()
150 regmap_write(regmap, 0x91, val[CLK]); in dphy_set_timing_reg()
157 regmap_write(regmap, 0x33, val[CLK]); in dphy_set_timing_reg()
163 regmap_write(regmap, 0x92, val[CLK]); in dphy_set_timing_reg()
170 regmap_write(regmap, 0x34, val[CLK]); in dphy_set_timing_reg()
222 u8 val[2]; in dphy_timing_config() local
239 val[DATA] = val[CLK]; in dphy_timing_config()
276 val[DATA] = val[CLK]; in dphy_timing_config()
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/drivers/spi/
A Dspi-armada-3700.c128 u32 val; in a3700_spi_auto_cs_unset() local
137 u32 val; in a3700_spi_activate_cs() local
147 u32 val; in a3700_spi_deactivate_cs() local
157 u32 val; in a3700_spi_pin_mode_set() local
187 u32 val; in a3700_spi_fifo_mode_set() local
200 u32 val; in a3700_spi_mode_set() local
220 u32 val; in a3700_spi_clock_set() local
233 val = val & ~A3700_SPI_CLK_PRESCALE_MASK; in a3700_spi_clock_set()
247 u32 val; in a3700_spi_bytelen_set() local
477 val = (val << 8) | a3700_spi->tx_buf[0]; in a3700_spi_header_set()
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/drivers/net/phy/mscc/
A Dmscc_ptp.c97 val <<= 16; in vsc85xx_ts_read_csr()
104 return val; in vsc85xx_ts_read_csr()
194 val = (val << 6) | sig_sel[pos]; in vsc85xx_ts_fsb_init()
347 u32 val; in vsc85xx_ts_eth_cmp1_sig() local
514 u32 val; in vsc85xx_ptp_cmp_init() local
544 u32 val; in vsc85xx_eth_cmp1_init() local
576 u32 val; in vsc85xx_ip_cmp1_init() local
617 u32 val; in vsc85xx_adjfine() local
651 u32 val; in __vsc85xx_gettime() local
703 u32 val; in __vsc85xx_settime() local
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/drivers/media/dvb-frontends/
A Dlgdt3306a.c185 u8 val; in lgdt3306a_set_reg_bit() local
226 u8 val; in lgdt3306a_mpeg_mode() local
264 u8 val; in lgdt3306a_mpeg_mode_polarity() local
290 u8 val; in lgdt3306a_mpeg_tristate() local
383 u8 val; in lgdt3306a_set_vsb() local
543 u8 val; in lgdt3306a_set_qam() local
817 u8 val; in lgdt3306a_init() local
1071 u8 val; in lgdt3306a_monitor_vsb() local
1161 val = val >> 2; in lgdt3306a_check_oper_mode()
1424 u8 val; in lgdt3306a_get_packet_error() local
[all …]
/drivers/phy/socionext/
A Dphy-uniphier-ahci.c76 u32 val; in uniphier_ahciphy_pro4_init() local
80 val &= ~CKCTRL0_NCY_MASK; in uniphier_ahciphy_pro4_init()
114 u32 val; in uniphier_ahciphy_pro4_power_on() local
119 val &= ~CKCTRL0_CK_OFF; in uniphier_ahciphy_pro4_power_on()
169 val |= CKCTRL0_CK_OFF; in uniphier_ahciphy_pro4_power_on()
177 u32 val; in uniphier_ahciphy_pro4_power_off() local
190 val |= CKCTRL0_CK_OFF; in uniphier_ahciphy_pro4_power_off()
199 u32 val; in uniphier_ahciphy_pxs2_enable() local
209 val |= CKCTRL_P0_RESET; in uniphier_ahciphy_pxs2_enable()
219 u32 val; in uniphier_ahciphy_pxs2_power_on() local
[all …]
/drivers/thunderbolt/
A Dusb4.c58 u32 val; in usb4_native_switch_op() local
168 u32 val; in usb4_switch_check_wakes() local
214 u32 val; in link_is_usb4() local
310 u32 val; in usb4_switch_configuration_valid() local
392 u32 val; in usb4_switch_lane_bonding_possible() local
1435 &val, sizeof(val)); in usb4_port_sb_op()
1454 USB4_SB_METADATA, &val, sizeof(val)); in usb4_port_set_router_offline()
1460 USB4_SB_OPCODE, &val, sizeof(val)); in usb4_port_set_router_offline()
1504 USB4_SB_OPCODE, &val, sizeof(val)); in usb4_port_enumerate_retimers()
2003 USB4_SB_OPCODE, &val, sizeof(val)); in usb4_port_retimer_nvm_authenticate()
[all …]
/drivers/net/wireless/realtek/rtw89/
A Dfw.h1916 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); in RTW89_SET_DISCONNECT_DETECT_ENABLE()
1921 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); in RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN()
1926 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); in RTW89_SET_DISCONNECT_DETECT_DISCONNECT()
1982 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); in RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE()
1987 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); in RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE()
1992 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); in RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE()
2927 *((__le32 *)cmd + 1) = val; in RTW89_SET_FWCMD_NOA_START_TIME()
2932 *((__le32 *)cmd + 2) = val; in RTW89_SET_FWCMD_NOA_INTERVAL()
2937 *((__le32 *)cmd + 3) = val; in RTW89_SET_FWCMD_NOA_DURATION()
2949 if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT)) in RTW89_SET_FWCMD_NOA_CTWINDOW()
[all …]
/drivers/power/supply/
A Dadp5061.c196 val /= 1000; in adp5061_set_input_current_limit()
199 val); in adp5061_set_input_current_limit()
213 val /= 1000; in adp5061_set_min_voltage()
216 val); in adp5061_set_min_voltage()
281 val /= 1000; in adp5061_set_max_voltage()
283 val = 4500; in adp5061_set_max_voltage()
305 val); in adp5061_set_const_chg_vmax()
326 val); in adp5061_set_const_chg_current()
378 val); in adp5061_set_prechg_current()
411 val); in adp5061_set_vweak_th()
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