| /drivers/iio/common/hid-sensors/ |
| A D | hid-sensor-attributes.c | 369 *val0 = scale0 * int_pow(10, exp); in adjust_exponent_nano()
381 *val0 += res; in adjust_exponent_nano()
386 *val0 = *val1 = 0; in adjust_exponent_nano()
390 *val0 = scale0 / divisor; in adjust_exponent_nano()
401 *val0 = scale0; in adjust_exponent_nano()
408 int *val0, int *val1) in hid_sensor_format_scale() argument
413 *val0 = 1; in hid_sensor_format_scale()
421 adjust_exponent_nano(val0, val1, in hid_sensor_format_scale()
563 int val0, val1; in hid_sensor_parse_common_attributes() local
566 ×tamp, &val0, &val1); in hid_sensor_parse_common_attributes()
[all …]
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| /drivers/gpu/drm/xe/ |
| A D | xe_hwmon.c | 147 u32 val0 = 0, val1 = 0; in xe_hwmon_pcode_read_power_limit() local
156 &val0, &val1); in xe_hwmon_pcode_read_power_limit()
160 channel, val0, val1, ret); in xe_hwmon_pcode_read_power_limit()
167 *uval = (val0 & PWR_LIM_EN) ? val0 : 0; in xe_hwmon_pcode_read_power_limit()
171 *uval = (val0 & PWR_LIM_EN) ? 1 : (val1 & PWR_LIM_EN) ? 1 : 0; in xe_hwmon_pcode_read_power_limit()
182 u32 val0, val1; in xe_hwmon_pcode_rmw_power_limit() local
191 &val0, &val1); in xe_hwmon_pcode_rmw_power_limit()
195 channel, val0, val1, ret); in xe_hwmon_pcode_rmw_power_limit()
198 val0 = (val0 & ~clr) | set; in xe_hwmon_pcode_rmw_power_limit()
208 val0, val1, PL_WRITE_MBX_TIMEOUT_MS); in xe_hwmon_pcode_rmw_power_limit()
[all …]
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| /drivers/soc/rockchip/ |
| A D | io-domain.c | 90 u32 val0, val1; in rk3568_iodomain_write() local
98 val0 = BIT(16 + b) | (is_3v3 ? 0 : BIT(b)); in rk3568_iodomain_write()
102 regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL2, val0); in rk3568_iodomain_write()
114 val0 = BIT(16 + b) | (is_3v3 ? 0 : BIT(b)); in rk3568_iodomain_write()
117 regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL0, val0); in rk3568_iodomain_write()
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| /drivers/net/dsa/microchip/ |
| A D | ksz9477_acl.c | 338 u8 vale, valf, val0; in ksz9477_acl_update_linkage() local
341 val0 = entry[KSZ9477_ACL_PORT_ACCESS_0]; in ksz9477_acl_update_linkage()
355 if (val0 != old_idx) { in ksz9477_acl_update_linkage()
357 old_idx, val0); in ksz9477_acl_update_linkage()
361 val0 = new_idx; in ksz9477_acl_update_linkage()
378 entry[KSZ9477_ACL_PORT_ACCESS_0] = val0; in ksz9477_acl_update_linkage()
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| /drivers/net/wireless/realtek/rtw89/ |
| A D | efuse_be.c | 225 u8 i, val0, val1; in rtw89_eeprom_parser_be() local
286 val0 = phy_map[phy_idx]; in rtw89_eeprom_parser_be()
293 log_map[log_idx - page_offset] = val0; in rtw89_eeprom_parser_be()
295 log_map[log_idx - page_offset] = val0; in rtw89_eeprom_parser_be()
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| /drivers/net/ethernet/chelsio/cxgb/ |
| A D | pm3393.c | 420 t1_tpi_read((mac)->adapter, OFFSET(name), &val0); \
423 (mac)->stats.stat_name = (u64)(val0 & 0xffff) | \
437 u32 val0, val1, val2, val3; in pm3393_update_statistics() local
444 pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0, &val0); in pm3393_update_statistics()
448 ro = ((u64)val0 & 0xffff) | (((u64)val1 & 0xffff) << 16) | in pm3393_update_statistics()
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| /drivers/edac/ |
| A D | versal_edac.c | 819 static void xddr_inject_data_ue_store(struct mem_ctl_info *mci, u32 val0, u32 val1) in xddr_inject_data_ue_store() argument
823 writel(val0, priv->ddrmc_baseaddr + ECCW0_FLIP0_OFFSET); in xddr_inject_data_ue_store()
824 writel(val0, priv->ddrmc_baseaddr + ECCW0_FLIP1_OFFSET); in xddr_inject_data_ue_store()
855 u32 val0 = 0, val1 = 0; in inject_data_ue_store() local
880 val0 = BIT(ue0); in inject_data_ue_store()
887 val0 |= BIT(ue1); in inject_data_ue_store()
899 xddr_inject_data_ue_store(mci, val0, val1); in inject_data_ue_store()
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| /drivers/media/platform/nxp/imx8-isi/ |
| A D | imx8-isi-hw.c | 173 u32 val, val0, val1; in mxc_isi_channel_set_crop() local
184 val0 = CHNL_CROP_ULC_X(dst->left) | CHNL_CROP_ULC_Y(dst->top); in mxc_isi_channel_set_crop()
187 mxc_isi_write(pipe, CHNL_CROP_ULC, val0); in mxc_isi_channel_set_crop()
188 mxc_isi_write(pipe, CHNL_CROP_LRC, val1 + val0); in mxc_isi_channel_set_crop()
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| /drivers/misc/sgi-gru/ |
| A D | grulib.h | 97 int val0; member
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| A D | grufault.c | 875 if (req.val0 < -1 || req.val0 >= GRU_CHIPLETS_PER_HUB || in gru_set_context_option()
881 gts->ts_user_chiplet_id = req.val0; in gru_set_context_option()
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| /drivers/gpu/drm/msm/adreno/ |
| A D | a6xx_gpu_state.h | 178 u32 val0; member
183 { .val0 = _base, .val1 = _type, .registers = _array, \
301 .val0 = _sel_reg, .val1 = _sel_val }
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| A D | a6xx_gpu_state.c | 1004 regs->registers[i] - (regs->val0 >> 2); in a6xx_get_crashdumper_hlsq_registers()
1043 if (regs->val0) in a6xx_get_crashdumper_registers()
1044 in += CRASHDUMP_WRITE(in, regs->val0, regs->val1); in a6xx_get_crashdumper_registers()
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| /drivers/media/usb/gspca/ |
| A D | ov519.c | 2914 unsigned char val0, val1; in ov51x_upload_quan_tables() local
2930 val0 = *pYTable++; in ov51x_upload_quan_tables()
2932 val0 &= 0x0f; in ov51x_upload_quan_tables()
2934 val0 |= val1 << 4; in ov51x_upload_quan_tables()
2935 reg_w(sd, reg, val0); in ov51x_upload_quan_tables()
2937 val0 = *pUVTable++; in ov51x_upload_quan_tables()
2939 val0 &= 0x0f; in ov51x_upload_quan_tables()
2941 val0 |= val1 << 4; in ov51x_upload_quan_tables()
2942 reg_w(sd, reg + size, val0); in ov51x_upload_quan_tables()
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| /drivers/media/pci/intel/ipu6/ |
| A D | ipu6-isys.h | 67 u8 val0; member
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| A D | ipu6-isys.c | 592 ltr = ltrdid.lut_ltr.bits.val0; in update_watermark_setting()
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| /drivers/thunderbolt/ |
| A D | icm.c | 1880 u32 val0, val1; in icm_reset_phy_port() local
1898 ret = pcie2cio_read(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, &val0); in icm_reset_phy_port()
1905 state0 = val0 & PHY_PORT_CS1_LINK_STATE_MASK; in icm_reset_phy_port()
1914 val0 |= PHY_PORT_CS1_LINK_DISABLE; in icm_reset_phy_port()
1915 ret = pcie2cio_write(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, val0); in icm_reset_phy_port()
1927 ret = pcie2cio_read(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, &val0); in icm_reset_phy_port()
1934 val0 &= ~PHY_PORT_CS1_LINK_DISABLE; in icm_reset_phy_port()
1935 ret = pcie2cio_write(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, val0); in icm_reset_phy_port()
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| /drivers/clk/nxp/ |
| A D | clk-lpc32xx.c | 373 static inline bool pll_is_valid(u64 val0, u64 val1, u64 min, u64 max) in pll_is_valid() argument
375 return (val0 >= (val1 * min) && val0 <= (val1 * max)); in pll_is_valid()
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| /drivers/infiniband/hw/erdma/ |
| A D | erdma_verbs.c | 1421 u64 val0, val1; in alloc_db_resources() local
1445 ret = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), &val0, &val1, in alloc_db_resources()
1451 ctx->ext_db.sdb_off = ERDMA_GET(val0, ALLOC_DB_RESP_SDB); in alloc_db_resources()
1452 ctx->ext_db.rdb_off = ERDMA_GET(val0, ALLOC_DB_RESP_RDB); in alloc_db_resources()
1453 ctx->ext_db.cdb_off = ERDMA_GET(val0, ALLOC_DB_RESP_CDB); in alloc_db_resources()
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| /drivers/gpu/drm/bridge/ |
| A D | ite-it6505.c | 697 int val0, val1; in it6505_read_word() local
699 val0 = it6505_read(it6505, reg); in it6505_read_word()
700 if (val0 < 0) in it6505_read_word()
701 return val0; in it6505_read_word()
707 return (val1 << 8) | val0; in it6505_read_word()
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| /drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_ring.h | 460 uint32_t reg0, uint32_t val0,
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| /drivers/staging/media/ipu3/ |
| A D | ipu3-css.c | 454 u32 val0 = imgu_css_gdc_lut[0][i] & IMGU_GDC_LUT_MASK; in imgu_css_hw_init() local
459 writel(val0 | (val1 << 16), in imgu_css_hw_init()
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