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Searched refs:val1 (Results 1 – 25 of 94) sorted by relevance

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/drivers/iio/common/hid-sensors/
A Dhid-sensor-attributes.c128 if (*val1) in convert_from_vtf_format()
129 *val1 = sign * (*val1); in convert_from_vtf_format()
188 *val1 = *val2 = 0; in hid_sensor_read_samp_freq_value()
251 *val1 = *val2 = 0; in hid_sensor_read_raw_hyst_value()
256 val1, val2); in hid_sensor_read_raw_hyst_value()
297 val1, val2); in hid_sensor_write_raw_hyst_value()
328 val1, val2); in hid_sensor_write_raw_hyst_rel_value()
372 *val1 = 0; in adjust_exponent_nano()
402 *val1 = scale1; in adjust_exponent_nano()
414 *val1 = 0; in hid_sensor_format_scale()
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/drivers/iio/adc/
A Dmt6370-adc.c133 int chan, int *val1, int *val2) in mt6370_adc_read_scale() argument
142 *val1 = 5; in mt6370_adc_read_scale()
157 *val1 = mt6370_adc_get_ibus_scale(priv); in mt6370_adc_read_scale()
160 *val1 = 5000; in mt6370_adc_read_scale()
178 *val1 = 2375; in mt6370_adc_read_scale()
184 *val1 = mt6370_adc_get_ibat_scale(priv); in mt6370_adc_read_scale()
187 *val1 = 5000; in mt6370_adc_read_scale()
195 *val1 = 25; in mt6370_adc_read_scale()
198 *val1 = 10; in mt6370_adc_read_scale()
201 *val1 = 25; in mt6370_adc_read_scale()
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A Dmcp3422.c161 struct iio_chan_spec const *channel, int *val1, in mcp3422_read_raw() argument
172 err = mcp3422_read_channel(adc, channel, val1); in mcp3422_read_raw()
179 *val1 = 0; in mcp3422_read_raw()
184 *val1 = mcp3422_sample_rates[MCP3422_SAMPLE_RATE(adc->config)]; in mcp3422_read_raw()
195 struct iio_chan_spec const *channel, int val1, in mcp3422_write_raw() argument
207 if (val1 != 0) in mcp3422_write_raw()
225 switch (val1) { in mcp3422_write_raw()
/drivers/gpu/drm/i915/
A Dintel_pcode.c56 u32 *val, u32 *val1, in __snb_pcode_rw() argument
72 intel_uncore_write_fw(uncore, GEN6_PCODE_DATA1, val1 ? *val1 : 0); in __snb_pcode_rw()
86 if (is_read && val1) in __snb_pcode_rw()
87 *val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1); in __snb_pcode_rw()
95 int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1) in snb_pcode_read() argument
100 err = __snb_pcode_rw(uncore, mbox, val, val1, 500, 20, true); in snb_pcode_read()
277 int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1) in intel_pcode_read() argument
281 return snb_pcode_read(&i915->uncore, mbox, val, val1); in intel_pcode_read()
A Dintel_pcode.h14 int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1);
31 int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1);
/drivers/power/supply/
A Daxp20x_battery.c281 int ret = 0, reg, val1; in axp20x_battery_get_prop() local
306 &val1); in axp20x_battery_get_prop()
310 if (val1) { in axp20x_battery_get_prop()
323 if ((val1 & AXP209_FG_PERCENT) == 100) in axp20x_battery_get_prop()
331 &val1); in axp20x_battery_get_prop()
366 &val1, 1000); in axp20x_battery_get_prop()
367 val->intval = -val1; in axp20x_battery_get_prop()
749 if (val1 < 0 || val1 > AXP20X_V_OFF_MASK) in axp20x_set_voltage_min_design()
753 AXP20X_V_OFF_MASK, val1); in axp20x_set_voltage_min_design()
761 if (val1 < 0 || val1 > AXP717_V_OFF_MASK) in axp717_set_voltage_min_design()
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/drivers/iio/pressure/
A Dicp10100.c282 int64_t val1, val2; in icp10100_get_pressure() local
294 val1 = (int64_t)st->cal[0] * (int64_t)t_square; in icp10100_get_pressure()
296 val1 = (int64_t)st->cal[1] * (int64_t)t_square; in icp10100_get_pressure()
298 (int32_t)div_s64(val1, inv_quadr_factor); in icp10100_get_pressure()
299 val1 = (int64_t)st->cal[2] * (int64_t)t_square; in icp10100_get_pressure()
305 val1 = (int64_t)p_lut[0] * (int64_t)p_lut[1] * in icp10100_get_pressure()
314 c = div64_s64(val1, val2); in icp10100_get_pressure()
316 val1, val2, c); in icp10100_get_pressure()
317 val1 = (int64_t)p_calib[0] * (int64_t)p_lut[0] - in icp10100_get_pressure()
321 a = div64_s64(val1, val2); in icp10100_get_pressure()
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/drivers/hwtracing/coresight/
A Dcoresight-etm4x-sysfs.c956 unsigned long val1, val2; in addr_range_show() local
985 unsigned long val1, val2; in addr_range_store() local
996 if (val1 > val2) in addr_range_store()
1960 unsigned long val1, val2; in ctxid_masks_show() local
1972 val1 = config->ctxid_mask0; in ctxid_masks_show()
2175 unsigned long val1, val2; in vmid_masks_show() local
2187 val1 = config->vmid_mask0; in vmid_masks_show()
2242 config->vmid_mask0 = val1; in vmid_masks_store()
2246 config->vmid_mask0 = val1; in vmid_masks_store()
2251 config->vmid_mask0 = val1; in vmid_masks_store()
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/drivers/scsi/fnic/
A Dfnic_trace.c218 struct timespec64 val1, val2; in fnic_get_stats_data() local
221 ktime_get_real_ts64(&val1); in fnic_get_stats_data()
233 (s64)val1.tv_sec, val1.tv_nsec, in fnic_get_stats_data()
238 (s64)timespec64_sub(val1, stats->stats_timestamps.last_reset_time).tv_sec, in fnic_get_stats_data()
239 timespec64_sub(val1, stats->stats_timestamps.last_reset_time).tv_nsec, in fnic_get_stats_data()
240 (s64)timespec64_sub(val1, stats->stats_timestamps.last_read_time).tv_sec, in fnic_get_stats_data()
241 timespec64_sub(val1, stats->stats_timestamps.last_read_time).tv_nsec); in fnic_get_stats_data()
243 stats->stats_timestamps.last_read_time = val1; in fnic_get_stats_data()
415 jiffies_to_timespec64(stats->misc_stats.last_isr_time, &val1); in fnic_get_stats_data()
441 (s64)val1.tv_sec, val1.tv_nsec, in fnic_get_stats_data()
/drivers/hwmon/
A Dmax6620.c251 u8 val1; in max6620_read() local
269 val1 = (data->target[channel] >> 3) & 0xff; in max6620_read()
272 target_reg[channel], val1); in max6620_read()
329 u8 val1; in max6620_write() local
375 val1 = (tach >> 3) & 0xff; in max6620_write()
377 ret = i2c_smbus_write_byte_data(client, target_reg[channel], val1); in max6620_write()
A Dw83792d.c238 #define TEMP_ADD_FROM_REG(val1, val2) \ argument
239 ((((val1) & 0x80 ? (val1)-0x100 \
1313 int val1, val2; in w83792d_detect() local
1325 if (!(val1 & 0x07)) { /* is Bank0 */ in w83792d_detect()
1327 ((val1 & 0x80) && val2 != 0x5c)) in w83792d_detect()
1346 if (val1 != 0x7a || val2 != 0x5c) in w83792d_detect()
1359 int i, val1, err; in w83792d_probe() local
1392 if (!(val1 & 0x40)) { in w83792d_probe()
1398 if (!(val1 & 0x20)) { in w83792d_probe()
1405 if (val1 & 0x40) { in w83792d_probe()
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A Dw83781d.c848 int i, val1 = 0, id; in w83781d_detect_subclients() local
876 sc_addr[0] = 0x48 + (val1 & 0x07); in w83781d_detect_subclients()
885 sc_addr[1] = 0x48 + ((val1 >> 4) & 0x07); in w83781d_detect_subclients()
1086 int val1, val2; in w83781d_detect() local
1113 if (!(val1 & 0x07) && in w83781d_detect()
1124 if ((!(val1 & 0x80) && val2 == 0xa3) || in w83781d_detect()
1125 ((val1 & 0x80) && val2 == 0x5c)) { in w83781d_detect()
1153 if ((val1 == 0x10 || val1 == 0x11) && vendid == winbond) in w83781d_detect()
1155 else if (val1 == 0x30 && vendid == winbond) in w83781d_detect()
1159 else if (val1 == 0x31) in w83781d_detect()
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/drivers/net/ethernet/broadcom/bnx2x/
A Dbnx2x_self_test.c54 return (args->val1 == args->imm1); in peq()
59 return (args->val1 != args->imm1); in pneq()
80 return (args->val1 > args->imm1); in pgt()
85 return (args->val1 != args->val2); in pneq_r2()
2954 rec->pred_args.val1 = in bnx2x_idle_chk6()
3001 rec->pred_args.val1 = in bnx2x_idle_chk7()
3077 rec.pred_args.val1); in bnx2x_idle_chk()
3086 rec.pred_args.val1 = in bnx2x_idle_chk()
3116 rec.pred_args.val1 = in bnx2x_idle_chk()
3125 rec.pred_args.val1, in bnx2x_idle_chk()
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/drivers/platform/x86/
A Damilo-rfkill.c56 u8 val1 = blocked ? M7440_RADIO_OFF1 : M7440_RADIO_ON1; in amilo_m7440_rfkill_set_block() local
59 outb(val1, M7440_PORT1); in amilo_m7440_rfkill_set_block()
63 if (inb(M7440_PORT1) != val1 || inb(M7440_PORT2) != val2) in amilo_m7440_rfkill_set_block()
/drivers/spi/
A Dspi-uniphier.c131 u32 val1, val2; in uniphier_spi_set_mode() local
148 val1 = SSI_CKS_CKPHS | SSI_CKS_CKDLY; in uniphier_spi_set_mode()
153 val1 = 0; in uniphier_spi_set_mode()
158 val1 = SSI_CKS_CKINIT | SSI_CKS_CKDLY; in uniphier_spi_set_mode()
163 val1 = SSI_CKS_CKPHS | SSI_CKS_CKINIT; in uniphier_spi_set_mode()
171 writel(val1, priv->base + SSI_CKS); in uniphier_spi_set_mode()
174 val1 = 0; in uniphier_spi_set_mode()
176 val1 |= FIELD_PREP(SSI_TXWDS_TDTF_MASK, 1); in uniphier_spi_set_mode()
177 writel(val1, priv->base + SSI_TXWDS); in uniphier_spi_set_mode()
178 writel(val1, priv->base + SSI_RXWDS); in uniphier_spi_set_mode()
/drivers/extcon/
A Dextcon-fsa9480.c222 int val1, val2; in fsa9480_detect_dev() local
225 val1 = fsa9480_read_reg(usbsw, FSA9480_REG_DEV_T1); in fsa9480_detect_dev()
227 if (val1 < 0 || val2 < 0) { in fsa9480_detect_dev()
231 val = val2 << 8 | val1; in fsa9480_detect_dev()
233 dev_info(usbsw->dev, "dev1: 0x%x, dev2: 0x%x\n", val1, val2); in fsa9480_detect_dev()
/drivers/gpu/drm/amd/display/dc/dce120/
A Ddce120_timing_generator.c51 #define CRTC_REG_UPDATE_2(reg, field1, val1, field2, val2) \ argument
52 CRTC_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
54 #define CRTC_REG_UPDATE_3(reg, field1, val1, field2, val2, field3, val3) \ argument
55 …CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3…
57 #define CRTC_REG_UPDATE_4(reg, field1, val1, field2, val2, field3, val3, field4, val4) \ argument
58 …CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3…
60 #define CRTC_REG_UPDATE_5(reg, field1, val1, field2, val2, field3, val3, field4, val4, field5, val5… argument
66 #define CRTC_REG_SET_2(reg, field1, val1, field2, val2) \ argument
67 CRTC_REG_SET_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
69 #define CRTC_REG_SET_3(reg, field1, val1, field2, val2, field3, val3) \ argument
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/drivers/input/joystick/
A Dwalkera0701.c65 int val1, val2, val3, val4, val5, val6, val7, val8; in walkera0701_parse_frame() local
85 val1 = ((w->buf[0] & 7) * 256 + w->buf[1] * 16 + w->buf[2]) >> 2; in walkera0701_parse_frame()
86 val1 *= ((w->buf[0] >> 2) & 2) - 1; /* sign */ in walkera0701_parse_frame()
105 val1, val2, val3, val4, val5, val6, val7, val8, in walkera0701_parse_frame()
109 input_report_abs(w->input_dev, ABS_Y, val1); in walkera0701_parse_frame()
/drivers/media/usb/dvb-usb-v2/
A Dmxl111sf-demod.c377 u8 val1, val2, val3; in mxl111sf_demod_read_ber() local
382 ret = mxl111sf_demod_read_reg(state, V6_RS_AVG_ERRORS_LSB_REG, &val1); in mxl111sf_demod_read_ber()
392 *ber = CALCULATE_BER((val1 | (val2 << 8)), val3); in mxl111sf_demod_read_ber()
400 u8 val1, val2; in mxl111sf_demod_calc_snr() local
405 ret = mxl111sf_demod_read_reg(state, V6_SNR_RB_LSB_REG, &val1); in mxl111sf_demod_calc_snr()
412 *snr = CALCULATE_SNR(val1 | ((val2 & 0x03) << 8)); in mxl111sf_demod_calc_snr()
/drivers/staging/media/starfive/camss/
A Dstf-isp-hw-ops.c367 u32 val, val1; in stf_isp_config_raw_fmt() local
375 val1 = CTRL_SAT(0x0); in stf_isp_config_raw_fmt()
382 val1 = CTRL_SAT(0x2); in stf_isp_config_raw_fmt()
389 val1 = CTRL_SAT(0x3); in stf_isp_config_raw_fmt()
396 val1 = CTRL_SAT(0x1); in stf_isp_config_raw_fmt()
401 val1 = CTRL_SAT(0x1); in stf_isp_config_raw_fmt()
405 stf_isp_reg_set_bit(stfcamss, ISP_REG_ISP_CTRL_1, CTRL_SAT_MASK, val1); in stf_isp_config_raw_fmt()
/drivers/iio/light/
A Dlm3533-als.c490 u8 val1; member
511 ret = lm3533_als_get_hysteresis(indio_dev, als_attr->val1, in show_als_attr()
515 ret = lm3533_als_get_target(indio_dev, als_attr->val1, in show_als_attr()
519 ret = lm3533_als_get_threshold(indio_dev, als_attr->val1, in show_als_attr()
523 ret = lm3533_als_get_threshold(indio_dev, als_attr->val1, in show_als_attr()
550 ret = lm3533_als_set_target(indio_dev, als_attr->val1, in store_als_attr()
554 ret = lm3533_als_set_threshold(indio_dev, als_attr->val1, in store_als_attr()
558 ret = lm3533_als_set_threshold(indio_dev, als_attr->val1, in store_als_attr()
574 .val1 = _val1, \
/drivers/gpu/drm/xe/
A Dxe_hwmon.c147 u32 val0 = 0, val1 = 0; in xe_hwmon_pcode_read_power_limit() local
156 &val0, &val1); in xe_hwmon_pcode_read_power_limit()
160 channel, val0, val1, ret); in xe_hwmon_pcode_read_power_limit()
169 *uval = (val1 & PWR_LIM_EN) ? val1 : 0; in xe_hwmon_pcode_read_power_limit()
171 *uval = (val0 & PWR_LIM_EN) ? 1 : (val1 & PWR_LIM_EN) ? 1 : 0; in xe_hwmon_pcode_read_power_limit()
182 u32 val0, val1; in xe_hwmon_pcode_rmw_power_limit() local
191 &val0, &val1); in xe_hwmon_pcode_rmw_power_limit()
195 channel, val0, val1, ret); in xe_hwmon_pcode_rmw_power_limit()
200 val1 = (val1 & ~clr) | set; in xe_hwmon_pcode_rmw_power_limit()
208 val0, val1, PL_WRITE_MBX_TIMEOUT_MS); in xe_hwmon_pcode_rmw_power_limit()
[all …]
A Dxe_pcode.c123 int xe_pcode_read(struct xe_tile *tile, u32 mbox, u32 *val, u32 *val1) in xe_pcode_read() argument
128 err = pcode_mailbox_rw(tile, mbox, val, val1, 1, true, false); in xe_pcode_read()
343 int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1) in intel_pcode_read() argument
348 return xe_pcode_read(tile, mbox, val, val1); in intel_pcode_read()
/drivers/net/ethernet/intel/i40e/
A Di40e_hmc.h104 u32 val1, val2, val3; \
105 val1 = (u32)(upper_32_bits(pa)); \
112 wr32((hw), I40E_PFHMC_SDDATAHIGH, val1); \
/drivers/media/tuners/
A Dqt1010.c218 u8 i, val1, val2; in qt1010_init_meas1() local
238 val1 = val2; in qt1010_init_meas1()
244 __func__, reg, val1, val2); in qt1010_init_meas1()
245 } while (val1 != val2); in qt1010_init_meas1()
246 *retval = val1; in qt1010_init_meas1()

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