| /drivers/net/ethernet/neterion/ |
| A D | s2io.c | 3098 val64 = val64 | MDIO_CTRL_START_TRANS(0xE); in s2io_mdio_write() 3109 val64 = val64 | MDIO_CTRL_START_TRANS(0xE); in s2io_mdio_write() 3118 val64 = val64 | MDIO_CTRL_START_TRANS(0xE); in s2io_mdio_write() 3140 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr) in s2io_mdio_read() 3144 val64 = val64 | MDIO_CTRL_START_TRANS(0xE); in s2io_mdio_read() 3154 val64 = val64 | MDIO_CTRL_START_TRANS(0xE); in s2io_mdio_read() 3189 val64 = val64 >> (index * 0x2); in s2io_chk_xpak_counter() 3190 val64 = val64 + 1; in s2io_chk_xpak_counter() 3217 val64 = val64 << (index * 0x2); in s2io_chk_xpak_counter() 4322 val64 = val64 & (~ADAPTER_LED_ON); in s2io_txpic_intr_handle() [all …]
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| /drivers/hwtracing/coresight/ |
| A D | coresight-config.c | 27 *((u64 *)reg_csdev->driver_regval) = reg_csdev->reg_desc.val64; in cscfg_set_reg() 47 reg_csdev->reg_desc.val64 = *(u64 *)(reg_csdev->driver_regval); in cscfg_save_reg() 65 param_csdev->val64 = reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_64BIT; in cscfg_init_reg_param() 67 if (param_csdev->val64) in cscfg_init_reg_param() 68 reg_csdev->reg_desc.val64 = param_csdev->current_value; in cscfg_init_reg_param() 130 reg_csdev->reg_desc.val64 = reg_desc->val64; in cscfg_reset_feat() 169 if (param_csdev->val64) { in cscfg_update_presets() 172 param_csdev->reg_csdev->reg_desc.val64 = val; in cscfg_update_presets() 208 if (param_csdev->val64) { in cscfg_update_curr_params() 211 param_csdev->reg_csdev->reg_desc.val64 = val; in cscfg_update_curr_params()
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| A D | coresight-config.h | 79 u64 val64; member 182 bool val64; member
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| A D | coresight-cfg-pstop.c | 43 .val64 = 0xf00,
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| /drivers/gpu/drm/i915/gvt/ |
| A D | gtt.c | 251 &e->val64, 8); in gtt_get_entry64() 276 &e->val64, 8); in gtt_set_entry64() 381 return (e->val64 != 0); in gen8_gtt_test_present() 1076 se->val64 = ge->val64; in ppgtt_generate_shadow_entry() 1110 sub_se.val64 = se->val64; in split_2MB_gtt_entry() 1114 sub_se.val64 |= (se->val64 & _PAGE_PAT_LARGE) >> 5; in split_2MB_gtt_entry() 1352 old.val64 = new.val64 = 0; in sync_oos_page() 1360 if (old.val64 == new.val64 in sync_oos_page() 1366 new.val64, index); in sync_oos_page() 1709 se.val64 = 0; in invalidate_ppgtt_mm() [all …]
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| /drivers/pci/ |
| A D | of_property.c | 112 u64 val64; in of_pci_prop_ranges() local 147 val64 = resource_size(&res[j]); in of_pci_prop_ranges() 148 rp[i].size[0] = upper_32_bits(val64); in of_pci_prop_ranges() 149 rp[i].size[1] = lower_32_bits(val64); in of_pci_prop_ranges() 420 u64 val64; in of_pci_host_bridge_prop_ranges() local 451 val64 = res->start; in of_pci_host_bridge_prop_ranges() 458 ranges[ranges_sz++] = upper_32_bits(val64); in of_pci_host_bridge_prop_ranges() 459 ranges[ranges_sz++] = lower_32_bits(val64); in of_pci_host_bridge_prop_ranges() 462 val64 = resource_size(res); in of_pci_host_bridge_prop_ranges() 463 ranges[ranges_sz] = upper_32_bits(val64); in of_pci_host_bridge_prop_ranges() [all …]
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| /drivers/iio/imu/inv_icm42600/ |
| A D | inv_icm42600_gyro.c | 402 s64 val64; in inv_icm42600_gyro_read_offset() local 462 if (val64 >= 0) in inv_icm42600_gyro_read_offset() 463 val64 += 2048 * 180 / 2; in inv_icm42600_gyro_read_offset() 465 val64 -= 2048 * 180 / 2; in inv_icm42600_gyro_read_offset() 466 bias = div_s64(val64, 2048 * 180); in inv_icm42600_gyro_read_offset() 478 s64 val64, min, max; in inv_icm42600_gyro_write_offset() local 506 if (val64 < min || val64 > max) in inv_icm42600_gyro_write_offset() 516 val64 = val64 * 180LL * 2048LL; in inv_icm42600_gyro_write_offset() 518 if (val64 >= 0) in inv_icm42600_gyro_write_offset() 519 val64 += 3141592653LL * 64LL / 2LL; in inv_icm42600_gyro_write_offset() [all …]
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| A D | inv_icm42600_accel.c | 699 s64 val64; in inv_icm42600_accel_read_offset() local 759 if (val64 >= 0) in inv_icm42600_accel_read_offset() 760 val64 += 10000LL / 2LL; in inv_icm42600_accel_read_offset() 762 val64 -= 10000LL / 2LL; in inv_icm42600_accel_read_offset() 763 bias = div_s64(val64, 10000L); in inv_icm42600_accel_read_offset() 775 s64 val64; in inv_icm42600_accel_write_offset() local 804 if (val64 < min || val64 > max) in inv_icm42600_accel_write_offset() 814 val64 = val64 * 10000LL; in inv_icm42600_accel_write_offset() 816 if (val64 >= 0) in inv_icm42600_accel_write_offset() 817 val64 += 9806650 * 5 / 2; in inv_icm42600_accel_write_offset() [all …]
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| /drivers/net/ethernet/marvell/octeon_ep/ |
| A D | octep_main.h | 346 #define octep_write_csr64(octep_dev, reg_off, val64) \ argument 347 writeq(val64, (octep_dev)->mmio[0].hw_addr + (reg_off)) 367 u64 val64; in OCTEP_PCI_WIN_READ() local 371 val64 = readq(oct->pci_win_regs.pci_win_rd_data); in OCTEP_PCI_WIN_READ() 374 "%s: reg: 0x%016llx val: 0x%016llx\n", __func__, addr, val64); in OCTEP_PCI_WIN_READ() 376 return val64; in OCTEP_PCI_WIN_READ()
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| /drivers/thermal/intel/ |
| A D | intel_powerclamp.c | 435 u64 val64; in powerclamp_adjust_controls() local 445 val64 = 100*(msr_now-msr_last); in powerclamp_adjust_controls() 446 do_div(val64, (tsc_now-tsc_last)); in powerclamp_adjust_controls() 447 current_ratio = val64; in powerclamp_adjust_controls() 505 u64 val64; in poll_pkg_cstate() local 515 val64 = 100 * (msr_now - msr_last); in poll_pkg_cstate() 516 do_div(val64, (tsc_now - tsc_last)); in poll_pkg_cstate() 517 pkg_cstate_ratio_cur = val64; in poll_pkg_cstate()
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| /drivers/infiniband/hw/hfi1/ |
| A D | pio_copy.c | 108 val.val64 = 0; in pio_copy() 110 writeq(val.val64, dest); in pio_copy() 186 pbuf->carry.val64 = 0; in read_low_bytes() 223 temp = pbuf->carry.val64 | (new << mshift(pbuf->carry_bytes)); in merge_write8() 225 pbuf->carry.val64 = new >> zshift(pbuf->carry_bytes); in merge_write8() 233 writeq(carry.val64, dest); in carry8_write8() 245 writeq(pbuf->carry.val64, dest); in carry_write8()
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| /drivers/iio/common/cros_ec_sensors/ |
| A D | cros_ec_sensors.c | 42 s64 val64; in cros_ec_sensors_read() local 105 val64 = st->core.resp->sensor_range.ret; in cros_ec_sensors_read() 112 *val = div_s64(val64 * 980665, 10); in cros_ec_sensors_read() 123 *val2 = div_s64(val64 * 3141592653ULL, in cros_ec_sensors_read() 132 *val = val64; in cros_ec_sensors_read()
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| /drivers/iio/light/ |
| A D | cros_ec_light_prox.c | 45 s64 val64; in cros_ec_light_prox_read() local 109 val64 = st->core.resp->sensor_range.ret; in cros_ec_light_prox_read() 110 *val = val64 >> 16; in cros_ec_light_prox_read() 111 *val2 = (val64 & 0xffff) * 100; in cros_ec_light_prox_read()
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| /drivers/vfio/pci/nvgrace-gpu/ |
| A D | main.c | 309 nvgrace_gpu_get_read_value(size_t bar_size, u64 flags, __le64 val64) in nvgrace_gpu_get_read_value() argument 313 tmp_val = le64_to_cpu(val64); in nvgrace_gpu_get_read_value() 337 __le64 val64; in nvgrace_gpu_read_config_emu() local 348 sizeof(val64), in nvgrace_gpu_read_config_emu() 354 sizeof(val64), in nvgrace_gpu_read_config_emu() 360 val64 = nvgrace_gpu_get_read_value(memregion->bar_size, in nvgrace_gpu_read_config_emu() 365 (void *)&val64 + register_offset, copy_count)) { in nvgrace_gpu_read_config_emu()
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| /drivers/iommu/iommufd/ |
| A D | ioas.c | 596 cmd->val64 = ictx->account_mode == IOPT_PAGES_ACCOUNT_MM; in iommufd_option_rlimit_mode() 609 if (cmd->val64 == 0) in iommufd_option_rlimit_mode() 611 else if (cmd->val64 == 1) in iommufd_option_rlimit_mode() 627 cmd->val64 = !ioas->iopt.disable_large_pages; in iommufd_ioas_option_huge_pages() 631 if (cmd->val64 == 0) in iommufd_ioas_option_huge_pages() 633 if (cmd->val64 == 1) { in iommufd_ioas_option_huge_pages()
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| A D | main.c | 384 if (copy_to_user(&((struct iommu_option __user *)ucmd->ubuffer)->val64, in iommufd_option() 385 &cmd->val64, sizeof(cmd->val64))) in iommufd_option() 462 IOCTL_OP(IOMMU_OPTION, iommufd_option, struct iommu_option, val64),
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| /drivers/gpu/drm/amd/amdgpu/ |
| A D | atom.c | 705 uint64_t val64; in atom_op_div32() local 713 val64 = dst; in atom_op_div32() 714 val64 |= ((uint64_t)ctx->ctx->divmul[1]) << 32; in atom_op_div32() 715 do_div(val64, src); in atom_op_div32() 716 ctx->ctx->divmul[0] = lower_32_bits(val64); in atom_op_div32() 717 ctx->ctx->divmul[1] = upper_32_bits(val64); in atom_op_div32() 830 uint64_t val64; in atom_op_mul32() local 837 val64 = (uint64_t)dst * (uint64_t)src; in atom_op_mul32() 838 ctx->ctx->divmul[0] = lower_32_bits(val64); in atom_op_mul32() 839 ctx->ctx->divmul[1] = upper_32_bits(val64); in atom_op_mul32()
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| /drivers/input/touchscreen/ |
| A D | tsc2007_core.c | 221 u64 val64; in tsc2007_probe_properties() local 237 if (!device_property_read_u64(dev, "ti,poll-period", &val64)) in tsc2007_probe_properties() 238 ts->poll_period = msecs_to_jiffies(val64); in tsc2007_probe_properties()
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| /drivers/iio/dac/ |
| A D | ad5791.c | 274 u64 val64; in ad5791_read_raw() local 290 val64 = (((u64)st->vref_neg_mv) << chan->scan_type.realbits); in ad5791_read_raw() 291 do_div(val64, st->vref_mv); in ad5791_read_raw() 292 *val = -val64; in ad5791_read_raw()
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| /drivers/net/ethernet/marvell/octeon_ep_vf/ |
| A D | octep_vf_main.h | 314 #define octep_vf_write_csr64(octep_vf_dev, reg_off, val64) \ argument 315 writeq(val64, (octep_vf_dev)->mmio.hw_addr + (reg_off))
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| /drivers/usb/early/ |
| A D | xhci-dbc.c | 40 u64 val64, sz64, mask64; in xdbc_map_pci_mmio() local 55 val64 = val & PCI_BASE_ADDRESS_MEM_MASK; in xdbc_map_pci_mmio() 65 val64 |= (u64)val << 32; in xdbc_map_pci_mmio() 86 xdbc.xhci_start = val64; in xdbc_map_pci_mmio() 88 base = early_ioremap(val64, sz64); in xdbc_map_pci_mmio()
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| /drivers/hv/ |
| A D | hv_kvp.c | 381 __u64 val64; in kvp_send_key() local 449 val64 = in_msg->body.kvp_set.data.value_u64; in kvp_send_key() 452 "%llu", val64) + 1; in kvp_send_key()
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| /drivers/net/ethernet/cavium/liquidio/ |
| A D | octeon_device.h | 736 #define octeon_write_csr64(oct_dev, reg_off, val64) \ argument 737 writeq(val64, (oct_dev)->mmio[0].hw_addr + (reg_off))
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| /drivers/misc/genwqe/ |
| A D | card_dev.c | 1087 put_user(val, &io->val64); in genwqe_ioctl() 1106 if (get_user(val, &io->val64)) in genwqe_ioctl() 1123 put_user(val, &io->val64); in genwqe_ioctl() 1142 if (get_user(val, &io->val64)) in genwqe_ioctl()
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| /drivers/accel/ivpu/ |
| A D | ivpu_hw_ip.c | 899 u64 val64; in soc_cpu_boot_40xx() local 907 val64 = vdev->fw->entry_point; in soc_cpu_boot_40xx() 908 val64 <<= ffs(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IMAGE_LOCATION_MASK) - 1; in soc_cpu_boot_40xx() 909 REGV_WR64(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val64); in soc_cpu_boot_40xx()
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