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Searched refs:vba (Results 1 – 25 of 29) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddisplay_mode_vba_20.c238 mode_lib->vba.DRAMSpeed * mode_lib->vba.NumberOfChannels * mode_lib->vba.DRAMChannelWidth, in dml20_recalculate()
2055 mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb], in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2369 if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 0) { in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2397 mode_lib->vba.ActiveDPPs = mode_lib->vba.ActiveDPPs + mode_lib->vba.DPPPerPlane[k]; in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2608 mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb], in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3401 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; in dml20_ModeSupportAndSystemConfigurationFull()
4799 …+ mode_lib->vba.cursor_bw[k] + mode_lib->vba.ReadBandwidth[k] + mode_lib->vba.meta_row_bw[k] + mod… in dml20_ModeSupportAndSystemConfigurationFull()
5097 mode_lib->vba.DCFCLK = mode_lib->vba.DCFCLKPerState[mode_lib->vba.VoltageLevel]; in dml20_ModeSupportAndSystemConfigurationFull()
5098 mode_lib->vba.DRAMSpeed = mode_lib->vba.DRAMSpeedPerState[mode_lib->vba.VoltageLevel]; in dml20_ModeSupportAndSystemConfigurationFull()
5099 mode_lib->vba.FabricClock = mode_lib->vba.FabricClockPerState[mode_lib->vba.VoltageLevel]; in dml20_ModeSupportAndSystemConfigurationFull()
[all …]
A Ddisplay_mode_vba_20v2.c262 mode_lib->vba.DRAMSpeed * mode_lib->vba.NumberOfChannels * mode_lib->vba.DRAMChannelWidth, in dml20v2_recalculate()
2091 mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb], in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2126 …vba.DPPCLK[k], mode_lib->vba.DISPCLK, mode_lib->vba.PixelClock[k], mode_lib->vba.DSCDelay[k], mode… in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2128 …mode_lib->vba.SwathWidthY[k] / mode_lib->vba.HRatio[k], mode_lib->vba.OutputFormat[k], mode_lib->v… in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2129 …vba.SwathWidthSingleDPPY[k], mode_lib->vba.BytePerPixelDETY[k], mode_lib->vba.BytePerPixelDETC[k],… in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2431 mode_lib->vba.ActiveDPPs = mode_lib->vba.ActiveDPPs + mode_lib->vba.DPPPerPlane[k]; in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2681 mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb], in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3508 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; in dml20v2_ModeSupportAndSystemConfigurationFull()
5213 mode_lib->vba.DCFCLK = mode_lib->vba.DCFCLKPerState[mode_lib->vba.VoltageLevel]; in dml20v2_ModeSupportAndSystemConfigurationFull()
5214 mode_lib->vba.DRAMSpeed = mode_lib->vba.DRAMSpeedPerState[mode_lib->vba.VoltageLevel]; in dml20v2_ModeSupportAndSystemConfigurationFull()
[all …]
A Ddcn20_fpu.c1165 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] in dcn20_calculate_dlg_params()
1226 …bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] … in dcn20_calculate_dlg_params()
1747 …pe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml… in dcn20_calculate_wm()
1751 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; in dcn20_calculate_wm()
1754 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]; in dcn20_calculate_wm()
1760 …context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from… in dcn20_calculate_wm()
2067 …dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_st… in dcn20_validate_bandwidth_internal()
2257 …_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.d… in dcn21_calculate_wm()
2261 … context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; in dcn21_calculate_wm()
2270 …context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_… in dcn21_calculate_wm()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddisplay_mode_vba_32.c207 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
573 mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP + mode_lib->vba.DPPPerPlane[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
672 …vba.NumberOfCursors[k] * mode_lib->vba.CursorWidth[k][0] * mode_lib->vba.CursorBPP[k][0] / 8 / (mo… in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1545 mode_lib->vba.HTotal, mode_lib->vba.VTotal, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1834 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; in dml32_ModeSupportAndSystemConfigurationFull()
1836 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k] in dml32_ModeSupportAndSystemConfigurationFull()
1906 mode_lib->vba.htaps[k], mode_lib->vba.HTAPsChroma[k], mode_lib->vba.vtaps[k], in dml32_ModeSupportAndSystemConfigurationFull()
2646 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; in dml32_ModeSupportAndSystemConfigurationFull()
3733 mode_lib->vba.DRAMSpeed = mode_lib->vba.DRAMSpeedPerState[mode_lib->vba.VoltageLevel]; in dml32_ModeSupportAndSystemConfigurationFull()
3735 mode_lib->vba.SOCCLK = mode_lib->vba.SOCCLKPerState[mode_lib->vba.VoltageLevel]; in dml32_ModeSupportAndSystemConfigurationFull()
[all …]
A Ddcn32_fpu.c282 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch() local
481 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn32_set_phantom_stream_timing() local
520 num_dpp = vba->NoOfDPP[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]]; in dcn32_set_phantom_stream_timing()
607 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn32_assign_subvp_pipe() local
636 …(vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_pla… in dcn32_assign_subvp_pipe()
637 …(vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_pla… in dcn32_assign_subvp_pipe()
1042 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in subvp_validate_static_schedulability() local
1446 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn32_full_validate_bw_helper() local
1545 if (vba->ModeSupport[i][vba->maxMpcComb]) { in dcn32_full_validate_bw_helper()
1734 …if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_… in dcn32_calculate_dlg_params()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/
A Ddisplay_mode_vba.c545 mode_lib->vba.pipe_plane[j] = mode_lib->vba.NumberOfActivePlanes; in fetch_pipe_params()
547 mode_lib->vba.SourceScan[mode_lib->vba.NumberOfActivePlanes] = in fetch_pipe_params()
549 mode_lib->vba.ViewportWidth[mode_lib->vba.NumberOfActivePlanes] = in fetch_pipe_params()
609 mode_lib->vba.DCCEnable[mode_lib->vba.NumberOfActivePlanes] = in fetch_pipe_params()
625 mode_lib->vba.OutputFormat[mode_lib->vba.NumberOfActivePlanes] = in fetch_pipe_params()
627 mode_lib->vba.OutputBpp[mode_lib->vba.NumberOfActivePlanes] = in fetch_pipe_params()
629 mode_lib->vba.Output[mode_lib->vba.NumberOfActivePlanes] = in fetch_pipe_params()
1057 mode_lib->vba.PixelClock[k] = 2 * mode_lib->vba.PixelClock[k]; in PixelClockAdjustmentForProgressiveToInterlaceUnit()
1084 …mode_lib->vba.ReturnBW = mode_lib->vba.ReturnBWPerState[mode_lib->vba.VoltageLevel][mode_lib->vba.… in ModeSupportAndSystemConfiguration()
1086 mode_lib->vba.ReturnBW = mode_lib->vba.ReturnBWPerState[mode_lib->vba.VoltageLevel][0]; in ModeSupportAndSystemConfiguration()
[all …]
A Ddisplay_mode_lib.c291 for (i = mode_lib->vba.soc.num_states; i >= 0; i--) { in dml_log_mode_support_params()
298 … : [%s, %s]\n", mode_lib->vba.ViewportSizeSupport[i][0] ? "Supported" : "NOT Supported… in dml_log_mode_support_params()
304 … : [%s, %s]\n", mode_lib->vba.ROBSupport[i][0] ? "Supported" : "NOT Supported", m… in dml_log_mode_support_params()
305 … : [%s, %s]\n", mode_lib->vba.DISPCLK_DPPCLK_Support[i][0] ? "Supported" : "NOT Support… in dml_log_mode_support_params()
306 … : [%s, %s]\n", mode_lib->vba.TotalAvailablePipesSupport[i][0] ? "Supported" : "NOT Suppo… in dml_log_mode_support_params()
311 … : [%s, %s]\n", mode_lib->vba.PrefetchSupported[i][0] ? "Supported" : "NOT Supported"… in dml_log_mode_support_params()
312 … : [%s, %s]\n", mode_lib->vba.DynamicMetadataSupported[i][0] ? "Supported" : "NOT Suppor… in dml_log_mode_support_params()
314 … : [%s, %s]\n", mode_lib->vba.VRatioInPrefetchSupported[i][0] ? "Supported" : "NOT Suppor… in dml_log_mode_support_params()
315 …ded : [%s, %s]\n", mode_lib->vba.PTEBufferSizeNotExceeded[i][0] ? "Supported" : "NOT Suppor… in dml_log_mode_support_params()
317 …dml_print("DML SUPPORT: HostVMEnable : %d\n", mode_lib->vba.HostVMEnabl… in dml_log_mode_support_params()
[all …]
A Ddisplay_mode_lib.h89 struct vba_vars_st vba; member
/drivers/gpu/drm/amd/display/dc/dml/dcn21/
A Ddisplay_mode_vba_21.c2101 mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2246 …mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m] / 8.0 / (mode_lib->vba.HTotal[k] /… in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2416 mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2562 if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 0) { in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2614 mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3635 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; in dml21_ModeSupportAndSystemConfigurationFull()
3637 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k] / 2.0; in dml21_ModeSupportAndSystemConfigurationFull()
5220 mode_lib->vba.DCFCLK = mode_lib->vba.DCFCLKPerState[mode_lib->vba.VoltageLevel]; in dml21_ModeSupportAndSystemConfigurationFull()
5221 mode_lib->vba.DRAMSpeed = mode_lib->vba.DRAMSpeedPerState[mode_lib->vba.VoltageLevel]; in dml21_ModeSupportAndSystemConfigurationFull()
5222 mode_lib->vba.FabricClock = mode_lib->vba.FabricClockPerState[mode_lib->vba.VoltageLevel]; in dml21_ModeSupportAndSystemConfigurationFull()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddcn30_fpu.c309 int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; in dcn30_fpu_calculate_wm_and_dlg()
311 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
344 maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; in dcn30_fpu_calculate_wm_and_dlg()
345 dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
346 …pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_ch… in dcn30_fpu_calculate_wm_and_dlg()
409 unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed; in dcn30_fpu_calculate_wm_and_dlg()
415 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] == in dcn30_fpu_calculate_wm_and_dlg()
473 context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod; in dcn30_fpu_calculate_wm_and_dlg()
500 context->bw_ctx.dml.vba.DRAMSpeed <= 1700 && in dcn30_fpu_calculate_wm_and_dlg()
501 context->bw_ctx.dml.vba.DRAMSpeed >= 1500) { in dcn30_fpu_calculate_wm_and_dlg()
[all …]
A Ddisplay_mode_vba_30.c3081 mode_lib->vba.SourceScan, in DisplayPipeConfiguration()
3100 mode_lib->vba.HActive, in DisplayPipeConfiguration()
3101 mode_lib->vba.HRatio, in DisplayPipeConfiguration()
3102 mode_lib->vba.HRatioChroma, in DisplayPipeConfiguration()
3103 mode_lib->vba.DPPPerPlane, in DisplayPipeConfiguration()
3108 mode_lib->vba.SwathHeightY, in DisplayPipeConfiguration()
3109 mode_lib->vba.SwathHeightC, in DisplayPipeConfiguration()
5260 mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP + DPPPerPlane[k]; in CalculateWatermarksAndDRAMSpeedChangeSupport()
5262 mode_lib->vba.TotalDCCActiveDPP = mode_lib->vba.TotalDCCActiveDPP + DPPPerPlane[k]; in CalculateWatermarksAndDRAMSpeedChangeSupport()
5273 mode_lib->vba.TotalActiveWriteback = mode_lib->vba.TotalActiveWriteback + 1; in CalculateWatermarksAndDRAMSpeedChangeSupport()
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_mall_phantom.c235 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in assign_subvp_pipe() local
257 …vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plan… in assign_subvp_pipe()
604 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dml2_svp_validate_static_schedulability() local
623 if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0 && in dml2_svp_validate_static_schedulability()
A Ddml2_wrapper.c494 context->bw_ctx.dml.vba.StutterPeriod = context->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterPeriod; in dml2_validate_and_build_resource()
498 if (context->bw_ctx.dml.vba.StutterPeriod < in_dc->debug.minimum_z8_residency_time && in dml2_validate_and_build_resource()
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddcn31_fpu.c471 …if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[context->bw_ctx.dml.vba.VoltageLevel][context->… in dcn315_update_soc_for_wm_a()
489 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
562 …context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_d… in dcn31_calculate_wm_and_dlg_fp()
/drivers/gpu/drm/amd/display/dc/resource/dcn30/
A Ddcn30_resource.c1639 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn30_internal_validate_bw() local
1645 context->bw_ctx.dml.vba.maxMpcComb = 0; in dcn30_internal_validate_bw()
1646 context->bw_ctx.dml.vba.VoltageLevel = 0; in dcn30_internal_validate_bw()
1647 context->bw_ctx.dml.vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive; in dcn30_internal_validate_bw()
1673 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported)) { in dcn30_internal_validate_bw()
1708 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled in dcn30_internal_validate_bw()
1777 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled; in dcn30_internal_validate_bw()
1863 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; in dcn30_internal_validate_bw()
1869 context->bw_ctx.dml.vba.VoltageLevel = vlevel; in dcn30_internal_validate_bw()
2085 …dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_st… in dcn30_validate_bandwidth()
/drivers/gpu/drm/amd/display/dc/resource/dcn21/
A Ddcn21_resource.c824 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn21_fast_validate_bw() local
830 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled in dcn21_fast_validate_bw()
854 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
878 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn21_fast_validate_bw()
882 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
904 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn21_fast_validate_bw()
/drivers/gpu/drm/amd/display/dc/dml/dcn35/
A Ddcn35_fpu.c568 context->bw_ctx.dml.vba.ODMCombinePolicy = in dcn35_populate_dml_pipes_from_context_fpu()
599 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; in dcn35_decide_zstate_support()
602 bool allow_z10 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z10_residency; in dcn35_decide_zstate_support()
615 (int)context->bw_ctx.dml.vba.StutterPeriod); in dcn35_decide_zstate_support()
/drivers/gpu/drm/amd/display/dc/core/
A Ddc_hw_sequencer.c635 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in set_p_state_switch_method() local
638 if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba) in set_p_state_switch_method()
642 if (vba->DRAMClockChangeSupport[vba->VoltageLevel][vba->maxMpcComb] != in set_p_state_switch_method()
/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource_helpers.c711 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn32_subvp_vblank_admissable() local
744 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp) in dcn32_subvp_vblank_admissable()
/drivers/gpu/drm/amd/display/dc/resource/dcn20/
A Ddcn20_resource.c1826 struct vba_vars_st *v = &context->bw_ctx.dml.vba; in dcn20_validate_apply_pipe_split_flags()
2054 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
2073 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) in dcn20_fast_validate_bw()
2083 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn20_fast_validate_bw()
2087 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
2110 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn20_fast_validate_bw()
/drivers/parisc/
A Dccio-dma.c546 ccio_io_pdir_entry(__le64 *pdir_ptr, space_t sid, unsigned long vba, in ccio_io_pdir_entry() argument
560 pa = lpa(vba); in ccio_io_pdir_entry()
585 asm volatile ("lci %%r0(%1), %0" : "=r" (ci) : "r" (vba)); in ccio_io_pdir_entry()
A Dsba_iommu.c572 sba_io_pdir_entry(__le64 *pdir_ptr, space_t sid, unsigned long vba, in sba_io_pdir_entry() argument
578 pa = lpa(vba); in sba_io_pdir_entry()
581 asm("lci 0(%1), %0" : "=r" (ci) : "r" (vba)); in sba_io_pdir_entry()
/drivers/gpu/drm/amd/display/dc/dml/dcn351/
A Ddcn351_fpu.c601 context->bw_ctx.dml.vba.ODMCombinePolicy = in dcn351_populate_dml_pipes_from_context_fpu()
632 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; in dcn351_decide_zstate_support()
/drivers/gpu/drm/amd/display/dc/dml/dcn314/
A Ddcn314_fpu.c425 context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1; in dcn314_populate_dml_pipes_from_context_fpu()
A Ddisplay_mode_vba_314.c1761 struct vba_vars_st *v = &mode_lib->vba;
1843 struct vba_vars_st *v = &mode_lib->vba;
2006 struct vba_vars_st *v = &mode_lib->vba;
3286 struct vba_vars_st *v = &mode_lib->vba;
3598 struct vba_vars_st *v = &mode_lib->vba;
3786 struct vba_vars_st *v = &mode_lib->vba;
3880 struct vba_vars_st *v = &mode_lib->vba;
5663 struct vba_vars_st *v = &mode_lib->vba;
5863 struct vba_vars_st *v = &mode_lib->vba;
6448 struct vba_vars_st *v = &mode_lib->vba;
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