| /drivers/gpu/drm/i915/display/ |
| A D | intel_crt.c | 702 u32 vblank, vblank_start, vblank_end; in intel_crt_load_detect() local
720 vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1; in intel_crt_load_detect()
753 if (vblank_start <= vactive && vblank_end >= vtotal) { in intel_crt_load_detect()
762 VBLANK_END(vblank_end - 1)); in intel_crt_load_detect()
766 if (vblank_start - vactive >= vtotal - vblank_end) in intel_crt_load_detect()
769 vsample = (vtotal + vblank_end) >> 1; in intel_crt_load_detect()
|
| A D | intel_vblank.c | 596 int vblank_end = mode->crtc_vblank_end; in intel_mode_vblank_end() local
599 vblank_end /= 2; in intel_mode_vblank_end()
601 return vblank_end; in intel_mode_vblank_end()
|
| A D | intel_vbt_defs.h | 627 u16 vblank_end; member
|
| A D | intel_display_regs.h | 382 #define VBLANK_END(vblank_end) REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end)) argument
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | display_rq_dlg_calc_20.c | 802 unsigned int vblank_end = dst->vblank_end; in dml20_rq_dlg_get_dlg_params() local
924 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml20_rq_dlg_get_dlg_params()
1030 <= vblank_end / 2.0) in dml20_rq_dlg_get_dlg_params()
1037 <= vblank_end) in dml20_rq_dlg_get_dlg_params()
1052 vblank_end); in dml20_rq_dlg_get_dlg_params()
|
| A D | display_rq_dlg_calc_20v2.c | 802 unsigned int vblank_end = dst->vblank_end; in dml20v2_rq_dlg_get_dlg_params() local
924 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml20v2_rq_dlg_get_dlg_params()
1031 <= vblank_end / 2.0) in dml20v2_rq_dlg_get_dlg_params()
1038 <= vblank_end) in dml20v2_rq_dlg_get_dlg_params()
1053 vblank_end); in dml20v2_rq_dlg_get_dlg_params()
|
| A D | dcn20_fpu.c | 1395 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start in dcn20_populate_dml_pipes_from_context()
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_rq_dlg_calc_21.c | 848 unsigned int vblank_end = dst->vblank_end; in dml_rq_dlg_get_dlg_params() local
970 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml_rq_dlg_get_dlg_params()
1070 <= vblank_end / 2.0) in dml_rq_dlg_get_dlg_params()
1077 <= vblank_end) in dml_rq_dlg_get_dlg_params()
1093 vblank_end); in dml_rq_dlg_get_dlg_params()
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | display_rq_dlg_calc_32.c | 232 unsigned int vblank_end = dst->vblank_end; in dml32_rq_dlg_get_dlg_reg() local
277 dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml32_rq_dlg_get_dlg_reg()
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | display_rq_dlg_calc_30.c | 914 unsigned int vblank_end = dst->vblank_end; in dml_rq_dlg_get_dlg_params() local
1041 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml_rq_dlg_get_dlg_params()
1131 <= vblank_end / 2.0) in dml_rq_dlg_get_dlg_params()
1138 <= vblank_end) in dml_rq_dlg_get_dlg_params()
1153 vblank_end); in dml_rq_dlg_get_dlg_params()
|
| /drivers/video/fbdev/ |
| A D | gbefb.c | 522 timing->vblank_end = timing->vtotal; in compute_gbe_timing()
561 SET_GBE_FIELD(VT_VBLANK, VBLANK_OFF, val, timing->vblank_end); in gbe_set_timing_info()
573 SET_GBE_FIELD(VT_VCMAP, VCMAP_OFF, val, timing->vblank_end); in gbe_set_timing_info()
581 temp = timing->vblank_start - timing->vblank_end - 1; in gbe_set_timing_info()
625 SET_GBE_FIELD(VT_VPIXEN, VPIXEN_ON, val, timing->vblank_end); in gbe_set_timing_info()
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_rq_dlg_calc_31.c | 876 unsigned int vblank_end = dst->vblank_end; in dml_rq_dlg_get_dlg_params() local
977 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml_rq_dlg_get_dlg_params()
1028 …art / 2.0 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end / 2.0) in dml_rq_dlg_get_dlg_params()
1033 …(vstartup_start - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end) in dml_rq_dlg_get_dlg_params()
|
| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | dml2_utils.c | 242 unsigned int hactive, vactive, hblank_start, vblank_start, hblank_end, vblank_end; in populate_pipe_ctx_dlg_params_from_dml() local
251 vblank_end = vblank_start - timing->v_addressable - timing->v_border_top - timing->v_border_bottom; in populate_pipe_ctx_dlg_params_from_dml()
265 pipe_ctx->pipe_dlg_param.vblank_end = vblank_end; in populate_pipe_ctx_dlg_params_from_dml()
|
| A D | dml_display_rq_dlg_calc.c | 214 dml_uint_t vblank_end = timing->VBlankEnd[plane_idx]; in dml_rq_dlg_get_dlg_reg() local
320 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml_rq_dlg_get_dlg_reg()
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | display_rq_dlg_calc_314.c | 961 unsigned int vblank_end = dst->vblank_end; in dml_rq_dlg_get_dlg_params() local
1062 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits in dml_rq_dlg_get_dlg_params()
1115 …art / 2.0 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end / 2.0) in dml_rq_dlg_get_dlg_params()
1120 …(vstartup_start - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end) in dml_rq_dlg_get_dlg_params()
|
| /drivers/gpu/drm/amd/display/dc/dml/ |
| A D | dml1_display_rq_dlg_calc.c | 1012 unsigned int vblank_end = e2e_pipe_param->pipe.dest.vblank_end; in dml1_rq_dlg_get_dlg_params() local
1159 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; /* 15 bits */ in dml1_rq_dlg_get_dlg_params()
1261 vblank_end); in dml1_rq_dlg_get_dlg_params()
|
| A D | display_mode_lib.c | 228 dml_print("DML PARAMS: vblank_end = %d\n", pipe_dest->vblank_end); in dml_log_pipe_params()
|
| A D | display_mode_structs.h | 515 unsigned int vblank_end; member
|
| /drivers/gpu/drm/amd/display/dc/hubp/dcn401/ |
| A D | dcn401_hubp.c | 157 unsigned int vblank_end = 0; in hubp401_vready_at_or_After_vsync() local
171 …vblank_end = vblank_start - timing->v_addressable - timing->v_border_top - timing->v_border_bottom; in hubp401_vready_at_or_After_vsync()
174 is_vready_at_or_after_vsync = (vstartup_lines - pixel_width / htotal) <= vblank_end; in hubp401_vready_at_or_After_vsync()
|
| /drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| A D | dcn_calcs.c | 440 input->dest.vblank_end = input->dest.vblank_start in pipe_ctx_to_e2e_pipe_params()
1232 pipe->pipe_dlg_param.vblank_end = asic_blank_end; in dcn_validate_bandwidth()
1258 hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end; in dcn_validate_bandwidth()
|
| /drivers/gpu/drm/amd/display/dmub/inc/ |
| A D | dmub_cmd.h | 1909 uint16_t vblank_end; member
2238 uint16_t vblank_end; member
2270 uint16_t vblank_end; member
|
| /drivers/gpu/drm/amd/display/dc/hubp/dcn10/ |
| A D | dcn10_hubp.c | 132 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { in hubp1_vready_workaround()
|
| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| A D | dml2_core_shared_types.h | 1577 unsigned int vblank_end; member
|
| /drivers/gpu/drm/amd/display/dc/hubp/dcn20/ |
| A D | dcn20_hubp.c | 188 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { in hubp2_vready_at_or_After_vsync()
|
| /drivers/gpu/drm/amd/display/dc/ |
| A D | dc_dmub_srv.c | 688 pipe_data->pipe_config.vblank_data.vblank_end = in populate_subvp_cmd_vblank_pipe_info()
|