| /drivers/gpu/drm/i915/display/ |
| A D | intel_vblank.c | 184 u32 vblank_start = mode->crtc_vblank_start; in __intel_get_crtc_scanline_from_timestamp() local
190 scanline = (scanline + vblank_start) % vtotal; in __intel_get_crtc_scanline_from_timestamp()
586 int vblank_start = mode->crtc_vblank_start; in intel_mode_vblank_start() local
589 vblank_start = DIV_ROUND_UP(vblank_start, 2); in intel_mode_vblank_start()
591 return vblank_start; in intel_mode_vblank_start()
672 evade->vblank_start = intel_vrr_vmin_vblank_start(crtc_state); in intel_vblank_evade_init()
674 evade->vblank_start = intel_vrr_vmax_vblank_start(crtc_state); in intel_vblank_evade_init()
678 evade->vblank_start = intel_mode_vblank_start(adjusted_mode); in intel_vblank_evade_init()
684 evade->min = evade->vblank_start - intel_usecs_to_scanlines(adjusted_mode, in intel_vblank_evade_init()
686 evade->max = evade->vblank_start - 1; in intel_vblank_evade_init()
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| A D | intel_crt.c | 702 u32 vblank, vblank_start, vblank_end; in intel_crt_load_detect() local
719 vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1; in intel_crt_load_detect()
753 if (vblank_start <= vactive && vblank_end >= vtotal) { in intel_crt_load_detect()
758 vblank_start = vsync_start; in intel_crt_load_detect()
761 VBLANK_START(vblank_start - 1) | in intel_crt_load_detect()
766 if (vblank_start - vactive >= vtotal - vblank_end) in intel_crt_load_detect()
767 vsample = (vblank_start + vactive) >> 1; in intel_crt_load_detect()
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| A D | intel_vblank.h | 20 int min, max, vblank_start; member
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| /drivers/media/platform/xilinx/ |
| A D | xilinx-vtc.h | 26 unsigned int vblank_start; member
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| A D | xilinx-vtc.c | 204 (config->vblank_start << XVTC_ACTIVE_VSIZE_SHIFT) | in xvtc_generator_start()
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| A D | xilinx-tpg.c | 192 .vblank_start = height, in xtpg_s_stream()
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| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | dml2_utils.c | 242 unsigned int hactive, vactive, hblank_start, vblank_start, hblank_end, vblank_end; in populate_pipe_ctx_dlg_params_from_dml() local
248 vblank_start = pipe_ctx->stream->timing.v_total - pipe_ctx->stream->timing.v_front_porch; in populate_pipe_ctx_dlg_params_from_dml()
251 vblank_end = vblank_start - timing->v_addressable - timing->v_border_top - timing->v_border_bottom; in populate_pipe_ctx_dlg_params_from_dml()
267 pipe_ctx->pipe_dlg_param.vblank_start = vblank_start; in populate_pipe_ctx_dlg_params_from_dml()
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| A D | dml2_translation_helper.c | 754 dml_uint_t hblank_start, vblank_start; in populate_dml_timing_cfg_from_stream_state() local
771 vblank_start = in->timing.v_total - in->timing.v_front_porch; in populate_dml_timing_cfg_from_stream_state()
772 out->VBlankEnd[location] = vblank_start in populate_dml_timing_cfg_from_stream_state()
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| /drivers/video/fbdev/ |
| A D | gbefb.c | 518 timing->vblank_start = var->yres; in compute_gbe_timing()
560 SET_GBE_FIELD(VT_VBLANK, VBLANK_ON, val, timing->vblank_start); in gbe_set_timing_info()
572 SET_GBE_FIELD(VT_VCMAP, VCMAP_ON, val, timing->vblank_start); in gbe_set_timing_info()
581 temp = timing->vblank_start - timing->vblank_end - 1; in gbe_set_timing_info()
626 SET_GBE_FIELD(VT_VPIXEN, VPIXEN_OFF, val, timing->vblank_start); in gbe_set_timing_info()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | display_rq_dlg_calc_20.c | 801 unsigned int vblank_start = dst->vblank_start; in dml20_rq_dlg_get_dlg_params() local
934 dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; in dml20_rq_dlg_get_dlg_params()
1051 vblank_start, in dml20_rq_dlg_get_dlg_params()
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| A D | display_rq_dlg_calc_20v2.c | 801 unsigned int vblank_start = dst->vblank_start; in dml20v2_rq_dlg_get_dlg_params() local
934 dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; in dml20v2_rq_dlg_get_dlg_params()
1052 vblank_start, in dml20v2_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_rq_dlg_calc_21.c | 847 unsigned int vblank_start = dst->vblank_start; in dml_rq_dlg_get_dlg_params() local
980 dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; in dml_rq_dlg_get_dlg_params()
1092 vblank_start, in dml_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | display_rq_dlg_calc_30.c | 913 unsigned int vblank_start = dst->vblank_start; in dml_rq_dlg_get_dlg_params() local
1048 dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; in dml_rq_dlg_get_dlg_params()
1152 vblank_start, in dml_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| A D | dml1_display_rq_dlg_calc.c | 1011 unsigned int vblank_start = e2e_pipe_param->pipe.dest.vblank_start; in dml1_rq_dlg_get_dlg_params() local
1172 dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; in dml1_rq_dlg_get_dlg_params()
1260 vblank_start, in dml1_rq_dlg_get_dlg_params()
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| A D | display_mode_lib.c | 227 dml_print("DML PARAMS: vblank_start = %d\n", pipe_dest->vblank_start); in dml_log_pipe_params()
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| A D | display_mode_structs.h | 514 unsigned int vblank_start; member
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| /drivers/gpu/drm/amd/display/dc/hubp/dcn401/ |
| A D | dcn401_hubp.c | 156 unsigned int vblank_start = 0; in hubp401_vready_at_or_After_vsync() local
170 vblank_start = timing->v_total - timing->v_front_porch; in hubp401_vready_at_or_After_vsync()
171 …vblank_end = vblank_start - timing->v_addressable - timing->v_border_top - timing->v_border_bottom; in hubp401_vready_at_or_After_vsync()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_rq_dlg_calc_31.c | 875 unsigned int vblank_start = dst->vblank_start; in dml_rq_dlg_get_dlg_params() local
982 dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; in dml_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | display_rq_dlg_calc_314.c | 960 unsigned int vblank_start = dst->vblank_start; in dml_rq_dlg_get_dlg_params() local
1067 dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; in dml_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| A D | dcn_calcs.c | 439 input->dest.vblank_start = input->dest.vtotal - pipe->stream->timing.v_front_porch; in pipe_ctx_to_e2e_pipe_params()
440 input->dest.vblank_end = input->dest.vblank_start in pipe_ctx_to_e2e_pipe_params()
1231 pipe->pipe_dlg_param.vblank_start = asic_blank_start; in dcn_validate_bandwidth()
1257 hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start; in dcn_validate_bandwidth()
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| /drivers/gpu/drm/ |
| A D | drm_vblank.c | 1002 u64 vblank_start; in drm_crtc_next_vblank_start() local
1016 vblank_start = DIV_ROUND_DOWN_ULL( in drm_crtc_next_vblank_start()
1019 *vblanktime = ktime_add(*vblanktime, ns_to_ktime(vblank_start)); in drm_crtc_next_vblank_start()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/ |
| A D | dml2_pmo_dcn4_fams2.c | 1687 stream_fams2_meta->vblank_start = timing->v_blank_end + timing->v_active; in build_fams2_meta_per_stream()
1741 stream_fams2_meta->vblank_start - in build_fams2_meta_per_stream()
1751 stream_fams2_meta->method_vblank.common.allow_start_otg_vline = stream_fams2_meta->vblank_start; in build_fams2_meta_per_stream()
1785 stream_fams2_meta->vblank_start - in build_fams2_meta_per_stream()
1794 stream_fams2_meta->vblank_start + in build_fams2_meta_per_stream()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| A D | dml21_translation_helper.c | 427 unsigned int hblank_start, vblank_start, min_hardware_refresh_in_uhz; in populate_dml21_timing_config_from_stream_state() local
449 vblank_start = stream->timing.v_total - stream->timing.v_front_porch; in populate_dml21_timing_config_from_stream_state()
451 timing->v_blank_end = vblank_start - stream->timing.v_addressable in populate_dml21_timing_config_from_stream_state()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/ |
| A D | dml2_internal_shared_types.h | 277 unsigned int vblank_start; member
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| /drivers/gpu/drm/amd/display/dmub/inc/ |
| A D | dmub_cmd.h | 1908 uint16_t vblank_start; member
2237 uint16_t vblank_start; member
2269 uint16_t vblank_start; member
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