Searched refs:vdpu_write (Results 1 – 12 of 12) sorted by relevance
| /drivers/media/platform/verisilicon/ |
| A D | hantro_g1.c | 24 vdpu_write(vpu, 0, G1_REG_INTERRUPT); in hantro_g1_irq()
25 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in hantro_g1_irq()
36 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT); in hantro_g1_reset()
37 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in hantro_g1_reset()
38 vdpu_write(vpu, 1, G1_REG_SOFT_RESET); in hantro_g1_reset()
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| A D | hantro_g2.c | 25 vdpu_write(vpu, status, G2_REG_INTERRUPT); in hantro_g2_check_idle()
40 vdpu_write(vpu, 0, G2_REG_INTERRUPT); in hantro_g2_irq()
41 vdpu_write(vpu, G2_REG_CONFIG_DEC_CLK_GATE_E, G2_REG_CONFIG); in hantro_g2_irq()
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| A D | rockchip_vpu_hw.c | 397 vdpu_write(vpu, 0, VDPU_REG_INTERRUPT); in rockchip_vpu2_vdpu_irq()
398 vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL); in rockchip_vpu2_vdpu_irq()
433 vdpu_write(vpu, 0, AV1_REG_INTERRUPT); in rk3588_vpu981_irq()
434 vdpu_write(vpu, AV1_REG_CONFIG_DEC_CLK_GATE_E, AV1_REG_CONFIG); in rk3588_vpu981_irq()
467 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT); in rk3066_vpu_dec_reset()
468 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in rk3066_vpu_dec_reset()
484 vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT); in rockchip_vpu2_dec_reset()
485 vdpu_write(vpu, 0, VDPU_REG_EN_FLAGS); in rockchip_vpu2_dec_reset()
486 vdpu_write(vpu, 1, VDPU_REG_SOFT_RESET); in rockchip_vpu2_dec_reset()
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| A D | hantro.h | 419 static __always_inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg) in vdpu_write() function
429 vdpu_write(vpu, addr & 0xffffffff, offset); in hantro_write_addr()
456 vdpu_write(vpu, vdpu_read_mask(vpu, reg, val), reg->base); in hantro_reg_write()
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| A D | imx8m_vpu_hw.c | 247 vdpu_write(vpu, 0, G1_REG_INTERRUPT); in imx8m_vpu_g1_irq()
248 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in imx8m_vpu_g1_irq()
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| A D | hantro_g1_h264_dec.c | 281 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT); in hantro_g1_h264_dec_run()
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| A D | hantro_g1_mpeg2_dec.c | 237 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT); in hantro_g1_mpeg2_dec_run()
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| A D | rockchip_vpu2_hw_mpeg2_dec.c | 245 vdpu_write(vpu, reg, VDPU_SWREG(57)); in rockchip_vpu2_mpeg2_dec_run()
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| A D | hantro_g1_vp8_dec.c | 508 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT); in hantro_g1_vp8_dec_run()
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| A D | rockchip_vpu2_hw_h264_dec.c | 488 vdpu_write(vpu, reg, VDPU_SWREG(57)); in rockchip_vpu2_h264_dec_run()
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| A D | hantro_g2_hevc_dec.c | 625 vdpu_write(vpu, G2_REG_INTERRUPT_DEC_E, G2_REG_INTERRUPT); in hantro_g2_hevc_dec_run()
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| A D | hantro_g2_vp9_dec.c | 911 vdpu_write(ctx->dev, G2_REG_INTERRUPT_DEC_E, G2_REG_INTERRUPT); in hantro_g2_vp9_dec_run()
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