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Searched refs:vdpu_write_relaxed (Results 1 – 7 of 7) sorted by relevance

/drivers/media/platform/verisilicon/
A Dhantro_g1_h264_dec.c49 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0); in set_params()
55 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1); in set_params()
65 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2); in set_params()
71 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL3); in set_params()
85 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL4); in set_params()
100 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL5); in set_params()
107 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL6); in set_params()
110 vdpu_write_relaxed(vpu, 0, G1_REG_ERR_CONC); in set_params()
113 vdpu_write_relaxed(vpu, in set_params()
120 vdpu_write_relaxed(vpu, 0, G1_REG_REF_BUF_CTRL); in set_params()
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A Drockchip_vpu2_hw_h264_dec.c207 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50)); in set_params()
211 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51)); in set_params()
216 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52)); in set_params()
219 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53)); in set_params()
227 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54)); in set_params()
233 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56)); in set_params()
248 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57)); in set_params()
253 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(59)); in set_params()
256 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(65)); in set_params()
316 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(74)); in set_ref()
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A Drockchip_vpu2_hw_mpeg2_dec.c114 vdpu_write_relaxed(vpu, addr, VDPU_REG_RLC_VLC_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
173 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50)); in rockchip_vpu2_mpeg2_dec_run()
177 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51)); in rockchip_vpu2_mpeg2_dec_run()
182 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52)); in rockchip_vpu2_mpeg2_dec_run()
185 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53)); in rockchip_vpu2_mpeg2_dec_run()
193 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54)); in rockchip_vpu2_mpeg2_dec_run()
199 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56)); in rockchip_vpu2_mpeg2_dec_run()
211 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57)); in rockchip_vpu2_mpeg2_dec_run()
217 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(120)); in rockchip_vpu2_mpeg2_dec_run()
225 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(122)); in rockchip_vpu2_mpeg2_dec_run()
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A Dhantro_g1_mpeg2_dec.c111 vdpu_write_relaxed(vpu, addr, G1_REG_RLC_VLC_BASE); in hantro_g1_mpeg2_dec_set_buffers()
119 vdpu_write_relaxed(vpu, addr, G1_REG_DEC_OUT_BASE); in hantro_g1_mpeg2_dec_set_buffers()
133 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE); in hantro_g1_mpeg2_dec_set_buffers()
181 vdpu_write_relaxed(vpu, reg, G1_SWREG(2)); in hantro_g1_mpeg2_dec_run()
194 vdpu_write_relaxed(vpu, reg, G1_SWREG(3)); in hantro_g1_mpeg2_dec_run()
200 vdpu_write_relaxed(vpu, reg, G1_SWREG(4)); in hantro_g1_mpeg2_dec_run()
208 vdpu_write_relaxed(vpu, reg, G1_SWREG(5)); in hantro_g1_mpeg2_dec_run()
212 vdpu_write_relaxed(vpu, reg, G1_SWREG(6)); in hantro_g1_mpeg2_dec_run()
221 vdpu_write_relaxed(vpu, reg, G1_SWREG(18)); in hantro_g1_mpeg2_dec_run()
225 vdpu_write_relaxed(vpu, reg, G1_SWREG(48)); in hantro_g1_mpeg2_dec_run()
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A Dhantro_g1_vp8_dec.c161 vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(0)); in cfg_lf()
306 vdpu_write_relaxed(vpu, in cfg_parts()
383 vdpu_write_relaxed(vpu, ref, G1_REG_ADDR_REF(0)); in cfg_ref()
393 vdpu_write_relaxed(vpu, ref, G1_REG_ADDR_REF(4)); in cfg_ref()
403 vdpu_write_relaxed(vpu, ref, G1_REG_ADDR_REF(5)); in cfg_ref()
426 vdpu_write_relaxed(vpu, reg, G1_REG_FWD_PIC(0)); in cfg_buffers()
464 vdpu_write_relaxed(vpu, reg, G1_REG_CONFIG); in hantro_g1_vp8_dec_run()
474 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0); in hantro_g1_vp8_dec_run()
483 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1); in hantro_g1_vp8_dec_run()
488 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2); in hantro_g1_vp8_dec_run()
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A Drockchip_vpu2_hw_vp8_dec.c302 vdpu_write_relaxed(vpu, reg, VDPU_REG_FILTER_MB_ADJ); in cfg_lf()
459 vdpu_write_relaxed(vpu, ref, VDPU_REG_VP8_ADDR_REF0); in cfg_ref()
469 vdpu_write_relaxed(vpu, ref, VDPU_REG_VP8_ADDR_REF2_5(2)); in cfg_ref()
492 vdpu_write_relaxed(vpu, ctx->vp8_dec.prob_tbl.dma, in cfg_buffers()
502 vdpu_write_relaxed(vpu, reg, VDPU_REG_VP8_SEGMENT_VAL); in cfg_buffers()
506 vdpu_write_relaxed(vpu, dst_dma, VDPU_REG_ADDR_DST); in cfg_buffers()
545 vdpu_write_relaxed(vpu, reg, VDPU_REG_EN_FLAGS); in rockchip_vpu2_vp8_dec_run()
553 vdpu_write_relaxed(vpu, reg, VDPU_REG_DATA_ENDIAN); in rockchip_vpu2_vp8_dec_run()
556 vdpu_write_relaxed(vpu, reg, VDPU_REG_AXI_CTRL); in rockchip_vpu2_vp8_dec_run()
559 vdpu_write_relaxed(vpu, reg, VDPU_REG_DEC_FORMAT); in rockchip_vpu2_vp8_dec_run()
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A Dhantro.h412 static __always_inline void vdpu_write_relaxed(struct hantro_dev *vpu, in vdpu_write_relaxed() function
463 vdpu_write_relaxed(vpu, vdpu_read_mask(vpu, reg, val), reg->base); in hantro_reg_write_relaxed()

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