| /drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| A D | dcn301_fpu.c | 292 static void calculate_wm_set_for_vlevel(int vlevel, in calculate_wm_set_for_vlevel() argument
301 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
303 pipes[0].clks_cfg.voltage = vlevel; in calculate_wm_set_for_vlevel()
304 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
419 int vlevel, vlevel_max; in dcn301_fpu_calculate_wm_and_dlg() local
431 vlevel = 0; in dcn301_fpu_calculate_wm_and_dlg()
433 vlevel = vlevel_max; in dcn301_fpu_calculate_wm_and_dlg()
438 vlevel = min(max(vlevel_req, 2), vlevel_max); in dcn301_fpu_calculate_wm_and_dlg()
443 vlevel = min(max(vlevel_req, 1), vlevel_max); in dcn301_fpu_calculate_wm_and_dlg()
449 vlevel = min(vlevel_req, vlevel_max); in dcn301_fpu_calculate_wm_and_dlg()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | dcn32_fpu.c | 279 int vlevel) in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch() argument
1039 int vlevel) in subvp_validate_static_schedulability() argument
1399 unsigned int *vlevel, in try_odm_power_optimization_and_revalidate() argument
1440 int *vlevel, in dcn32_full_validate_bw_helper() argument
1494 vlevel_temp = *vlevel; in dcn32_full_validate_bw_helper()
1532 *vlevel = i; in dcn32_full_validate_bw_helper()
1546 *vlevel = i; in dcn32_full_validate_bw_helper()
2277 vlevel = i; in dcn32_internal_validate_bw()
2288 *vlevel_out = vlevel; in dcn32_internal_validate_bw()
2305 int vlevel) in dcn32_calculate_wm_and_dlg_fpu() argument
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| A D | dcn32_fpu.h | 57 int vlevel);
65 int vlevel);
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | dcn20_fpu.c | 1145 int vlevel) in dcn20_calculate_dlg_params() argument
1735 int vlevel, in dcn20_calculate_wm() argument
1796 if (vlevel < 1) { in dcn20_calculate_wm()
1810 if (vlevel < 2) { in dcn20_calculate_wm()
1823 if (vlevel < 3) { in dcn20_calculate_wm()
2036 int vlevel = 0; in dcn20_validate_bandwidth_internal() local
2142 int vlevel, in dcn20_fpu_adjust_dppclk() argument
2244 int vlevel, vlevel_max; in dcn21_calculate_wm() local
2297 vlevel = 0; in dcn21_calculate_wm()
2299 vlevel = vlevel_max; in dcn21_calculate_wm()
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| A D | dcn20_fpu.h | 43 int vlevel);
53 int vlevel,
70 int vlevel,
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | dcn30_fpu.c | 307 int vlevel) in dcn30_fpu_calculate_wm_and_dlg() argument
311 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
334 context, pipes, pipe_cnt, vlevel); in dcn30_fpu_calculate_wm_and_dlg()
342 dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, in dcn30_fpu_calculate_wm_and_dlg()
353 pipes[0].clks_cfg.voltage = vlevel; in dcn30_fpu_calculate_wm_and_dlg()
362 if (vlevel == 0) { in dcn30_fpu_calculate_wm_and_dlg()
379 pipes[0].clks_cfg.voltage = vlevel; in dcn30_fpu_calculate_wm_and_dlg()
415 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] == in dcn30_fpu_calculate_wm_and_dlg()
511 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); in dcn30_fpu_calculate_wm_and_dlg()
624 int vlevel) in dcn30_find_dummy_latency_index_for_fw_based_mclk_switch() argument
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| A D | dcn30_fpu.h | 47 int vlevel);
67 int vlevel);
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| /drivers/soc/qcom/ |
| A D | spm.c | 333 unsigned int vlevel, volt_sel; in smp_set_vdd_v1_1() local
337 vlevel = volt_sel | 0x80; /* band */ in smp_set_vdd_v1_1()
355 vctl = FIELD_SET(vctl, SPM_VCTL_VLVL, vlevel); in smp_set_vdd_v1_1()
356 data0 = FIELD_SET(data0, SPM_PMIC_DATA_0_VLVL, vlevel); in smp_set_vdd_v1_1()
365 sts, sts == vlevel, in smp_set_vdd_v1_1()
368 dev_err_ratelimited(drv->dev, "timeout setting the voltage (%x %x)!\n", sts, vlevel); in smp_set_vdd_v1_1()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| A D | dcn20_resource.c | 1818 int vlevel, in dcn20_validate_apply_pipe_split_flags() argument
1881 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1882 if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 && in dcn20_validate_apply_pipe_split_flags()
1883 v->ModeSupport[vlevel][0]) in dcn20_validate_apply_pipe_split_flags()
1886 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
1887 vlevel = vlevel_split; in dcn20_validate_apply_pipe_split_flags()
2000 return vlevel; in dcn20_validate_apply_pipe_split_flags()
2015 int pipe_cnt, i, pipe_idx, vlevel; in dcn20_fast_validate_bw() local
2036 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw()
2039 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn20_fast_validate_bw()
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| A D | dcn20_resource.h | 129 int vlevel,
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| /drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| A D | dcn30_resource.h | 73 int vlevel);
106 display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel);
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| A D | dcn30_resource.c | 1638 int pipe_cnt, i, pipe_idx, vlevel = 0; in dcn30_internal_validate_bw() local
1668 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1669 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn30_internal_validate_bw()
1686 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
1689 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn30_internal_validate_bw()
1696 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1869 context->bw_ctx.dml.vba.VoltageLevel = vlevel; in dcn30_internal_validate_bw()
1870 *vlevel_out = vlevel; in dcn30_internal_validate_bw()
2031 int vlevel) in dcn30_calculate_wm_and_dlg() argument
2034 dcn30_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dcn30_calculate_wm_and_dlg()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | dcn31_fpu.c | 486 int vlevel) in dcn31_calculate_wm_and_dlg_fp() argument
489 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
506 pipes[0].clks_cfg.voltage = vlevel; in dcn31_calculate_wm_and_dlg_fp()
508 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
559 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); in dcn31_calculate_wm_and_dlg_fp()
562 …context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_d… in dcn31_calculate_wm_and_dlg_fp()
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| A D | dcn31_fpu.h | 45 int vlevel);
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| /drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| A D | dcn21_resource.c | 777 int pipe_cnt, i, pipe_idx, vlevel; in dcn21_fast_validate_bw() local
802 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
804 if (vlevel > context->bw_ctx.dml.soc.num_states) { in dcn21_fast_validate_bw()
814 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
815 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn21_fast_validate_bw()
819 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn21_fast_validate_bw()
878 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn21_fast_validate_bw()
909 *vlevel_out = vlevel; in dcn21_fast_validate_bw()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| A D | dcn31_resource.h | 47 int vlevel);
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| A D | dcn31_resource.c | 1733 int vlevel) in dcn31_calculate_wm_and_dlg() argument
1736 dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel); in dcn31_calculate_wm_and_dlg()
1769 int vlevel = 0; in dcn31_validate_bandwidth() local
1781 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, true); in dcn31_validate_bandwidth()
1798 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dcn31_validate_bandwidth()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource_helpers.c | 704 bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel) in dcn32_subvp_vblank_admissable() argument
744 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp) in dcn32_subvp_vblank_admissable()
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| A D | dcn32_resource.c | 1751 int vlevel = 0; in dml1_validate() local
1770 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode); in dml1_validate()
1786 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dml1_validate()
2055 int vlevel) in dcn32_calculate_wm_and_dlg() argument
2058 dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel); in dcn32_calculate_wm_and_dlg()
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| A D | dcn32_resource.h | 114 int vlevel);
183 bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel);
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| A D | core_types.h | 92 int vlevel);
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| /drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| A D | dcn314_resource.c | 1706 int vlevel = 0; in dcn314_validate_bandwidth() local
1719 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, false); in dcn314_validate_bandwidth()
1736 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dcn314_validate_bandwidth()
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