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Searched refs:vlv (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/i915/display/
A Di9xx_wm.c247 display->wm.vlv.cxsr = enable; in intel_set_memory_cxsr()
1717 &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_is_valid()
1719 &crtc_state->wm.vlv.fifo_state; in vlv_raw_plane_wm_is_valid()
1738 &crtc_state->wm.vlv.fifo_state; in _vlv_compute_pipe_wm()
1833 &crtc_state->wm.vlv.fifo_state; in vlv_compute_pipe_wm()
1861 &crtc_state->wm.vlv.fifo_state; in vlv_atomic_update_fifo()
2103 crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate; in vlv_initial_watermarks()
2119 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; in vlv_optimize_watermarks()
3951 &crtc_state->wm.vlv.fifo_state; in vlv_wm_get_hw_state()
4037 crtc_state->wm.vlv.optimal; in vlv_wm_sanitize()
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A Dintel_display_power_map.c204 .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
211 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01),
213 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23),
215 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01),
217 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23),
223 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
291 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
294 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
A Dintel_display_power_well.h73 } vlv; member
A Dintel_display_core.h268 struct vlv_wm_values vlv; member
A Dintel_display_types.h905 } vlv; member
1430 struct vlv_wm_state vlv; member
A Dintel_display_power_well.c1121 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; in vlv_set_power_well()
1170 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; in vlv_power_well_enabled()
/drivers/gpu/drm/i915/
A Dintel_clock_gating.c727 CG_FUNCS(vlv);

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