Searched refs:vlv_punit_read (Results 1 – 5 of 5) sorted by relevance
| /drivers/gpu/drm/i915/display/ |
| A D | intel_display_power_well.c | 1133 ((vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS) & mask) == state) in vlv_set_power_well()
1138 ctrl = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL); in vlv_set_power_well()
1147 vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL)); in vlv_set_power_well()
1181 state = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS) & mask; in vlv_power_well_enabled()
1195 ctrl = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL) & mask; in vlv_power_well_enabled()
1686 state = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe); in chv_pipe_power_well_enabled()
1699 ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); in chv_pipe_power_well_enabled()
1720 ((vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state) in chv_set_pipe_power_well()
1725 ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); in chv_set_pipe_power_well()
1734 vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM)); in chv_set_pipe_power_well()
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| A D | vlv_sideband.h | 141 static inline u32 vlv_punit_read(struct drm_device *drm, u32 addr) in vlv_punit_read() function
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| A D | i9xx_wm.c | 115 val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2); in chv_set_memory_dvfs()
124 if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2) & in chv_set_memory_dvfs()
138 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); in chv_set_memory_pm5()
3914 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); in vlv_wm_get_hw_state()
3927 val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2); in vlv_wm_get_hw_state()
3931 if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2) & in vlv_wm_get_hw_state()
3938 val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2); in vlv_wm_get_hw_state()
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| A D | intel_cdclk.c | 616 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); in vlv_get_cdclk()
701 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); in vlv_set_cdclk()
705 if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & in vlv_set_cdclk()
785 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); in chv_set_cdclk()
789 if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & in chv_set_cdclk()
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| A D | intel_display_power.c | 1888 ret = (vlv_punit_read(display->drm, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE; in vlv_punit_is_power_gated()
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