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Searched refs:vpu (Results 1 – 25 of 73) sorted by relevance

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/drivers/media/platform/mediatek/mdp3/
A Dmtk-mdp3-vpu.c52 dma_free_wc(dev, vpu->work_size, vpu->work, vpu->work_addr); in mdp_vpu_shared_mem_alloc()
55 dma_free_wc(dev, vpu->param_size, vpu->param, vpu->param_addr); in mdp_vpu_shared_mem_alloc()
70 if (vpu->param && vpu->param_addr) in mdp_vpu_shared_mem_free()
71 dma_free_wc(dev, vpu->param_size, vpu->param, vpu->param_addr); in mdp_vpu_shared_mem_free()
73 if (vpu->work && vpu->work_addr) in mdp_vpu_shared_mem_free()
74 dma_free_wc(dev, vpu->work_size, vpu->work, vpu->work_addr); in mdp_vpu_shared_mem_free()
76 if (vpu->config && vpu->config_addr) in mdp_vpu_shared_mem_free()
77 dma_free_wc(dev, vpu->config_size, vpu->config, vpu->config_addr); in mdp_vpu_shared_mem_free()
225 vpu->param, &vpu->param_addr, vpu->param_size, in mdp_vpu_dev_init()
226 vpu->work, &vpu->work_addr, vpu->work_size, in mdp_vpu_dev_init()
[all …]
/drivers/media/platform/mediatek/vpu/
A Dmtk_vpu.c278 vpu_running(vpu), vpu_cfg_readl(vpu, VPU_PC_REG), in vpu_dump_status()
279 vpu_cfg_readl(vpu, VPU_RA_REG), vpu_cfg_readl(vpu, VPU_SP_REG), in vpu_dump_status()
294 if (!vpu) { in vpu_ipi_register()
419 if (!vpu) { in vpu_wdt_reg_handler()
577 run = &vpu->run; in vpu_load_firmware()
644 strscpy(vpu->run.fw_ver, run->fw_ver, sizeof(vpu->run.fw_ver)); in vpu_init_ipi_handler()
769 vpu->recv_buf = vpu->reg.tcm + VPU_DTCM_OFFSET; in vpu_ipi_init()
770 vpu->send_buf = vpu->recv_buf + 1; in vpu_ipi_init()
798 queue_work(vpu->wdt.wq, &vpu->wdt.ws); in vpu_irq_handler()
820 vpu = devm_kzalloc(dev, sizeof(*vpu), GFP_KERNEL); in mtk_vpu_probe()
[all …]
/drivers/media/platform/mediatek/vcodec/decoder/
A Dvdec_vpu_if.c21 vpu->vsi = mtk_vcodec_fw_map_dm_addr(vpu->ctx->dev->fw_handler, in handle_init_ack_msg()
25 mtk_vdec_debug(vpu->ctx, "- vpu_inst_addr = 0x%x", vpu->inst_addr); in handle_init_ack_msg()
50 vpu->failure = 1; in handle_init_ack_msg()
70 vpu->failure = 1; in handle_get_param_msg_ack()
158 vpu->failure = 0; in vcodec_vpu_send_msg()
166 id = vpu->id; in vcodec_vpu_send_msg()
168 id = vpu->id; in vcodec_vpu_send_msg()
209 vpu->ctx->vpu_inst = vpu; in vpu_dec_init()
212 vpu->handler, "vdec", vpu->ctx->dev); in vpu_dec_init()
220 vpu->core_id, vpu->handler, in vpu_dec_init()
[all …]
/drivers/media/platform/amphion/
A Dvpu_drv.c44 if (atomic_inc_return(&vpu->ref_vpu) == 1 && vpu->res->setup) in vpu_dev_get()
45 vpu->res->setup(vpu); in vpu_dev_get()
56 vpu->res->setup_encoder(vpu); in vpu_enc_get()
67 vpu->res->setup_decoder(vpu); in vpu_dec_get()
77 vpu->mdev.dev = vpu->dev; in vpu_init_media_device()
81 vpu->v4l2_dev.mdev = &vpu->mdev; in vpu_init_media_device()
93 vpu = devm_kzalloc(dev, sizeof(*vpu), GFP_KERNEL); in vpu_probe()
94 if (!vpu) in vpu_probe()
117 if (!vpu->res) in vpu_probe()
131 ret = vpu_add_func(vpu, &vpu->decoder); in vpu_probe()
[all …]
A Dvpu_imx8q.c42 int vpu_imx8q_setup_dec(struct vpu_dev *vpu) in vpu_imx8q_setup_dec() argument
52 int vpu_imx8q_setup_enc(struct vpu_dev *vpu) in vpu_imx8q_setup_enc() argument
57 int vpu_imx8q_setup(struct vpu_dev *vpu) in vpu_imx8q_setup() argument
61 vpu_readl(vpu, offset + 0x108); in vpu_imx8q_setup()
64 vpu_writel(vpu, offset + 0x190, 0xffffffff); in vpu_imx8q_setup()
68 vpu_writel(vpu, XMEM_CONTROL, 0x102); in vpu_imx8q_setup()
70 vpu_readl(vpu, offset + 0x108); in vpu_imx8q_setup()
89 int vpu_imx8q_reset(struct vpu_dev *vpu) in vpu_imx8q_reset() argument
94 vpu_imx8q_reset_enc(vpu); in vpu_imx8q_reset()
95 vpu_imx8q_reset_dec(vpu); in vpu_imx8q_reset()
[all …]
A Dvpu_core.c243 core->vpu->get_vpu(core->vpu); in vpu_core_get_vpu()
245 core->vpu->get_enc(core->vpu); in vpu_core_get_vpu()
247 core->vpu->get_dec(core->vpu); in vpu_core_get_vpu()
299 core->vpu->put_enc(core->vpu); in vpu_core_put_vpu()
301 core->vpu->put_dec(core->vpu); in vpu_core_put_vpu()
302 core->vpu->put_vpu(core->vpu); in vpu_core_put_vpu()
419 vpu = inst->vpu; in vpu_inst_register()
530 vpu = inst->vpu; in vpu_get_resource()
624 if (!vpu) in vpu_core_probe()
633 core->vpu = vpu; in vpu_core_probe()
[all …]
/drivers/media/platform/mediatek/vcodec/encoder/
A Dvenc_vpu_if.c16 vpu->vsi = mtk_vcodec_fw_map_dm_addr(vpu->ctx->dev->fw_handler, in handle_enc_init_msg()
31 vpu->failure = 1; in handle_enc_init_msg()
70 if (!priv || !vpu) { in vpu_enc_ipi_handler()
84 if (vpu->failure) { in vpu_enc_ipi_handler()
85 mtk_venc_err(vpu->ctx, "vpu enc status failure %d", vpu->failure); in vpu_enc_ipi_handler()
106 vpu->signaled = 1; in vpu_enc_ipi_handler()
126 if (vpu->failure) in vpu_enc_send_msg()
138 vpu->signaled = 0; in vpu_enc_init()
139 vpu->failure = 0; in vpu_enc_init()
140 vpu->ctx->vpu_inst = vpu; in vpu_enc_init()
[all …]
/drivers/media/platform/verisilicon/
A Drockchip_vpu981_hw_av1_dec.c223 struct hantro_dev *vpu = ctx->dev; in rockchip_vpu981_av1_dec_tiles_free() local
256 struct hantro_dev *vpu = ctx->dev; in rockchip_vpu981_av1_dec_tiles_reallocate() local
322 struct hantro_dev *vpu = ctx->dev; in rockchip_vpu981_av1_dec_exit() local
364 struct hantro_dev *vpu = ctx->dev; in rockchip_vpu981_av1_dec_init() local
516 struct hantro_dev *vpu = ctx->dev; in rockchip_vpu981_av1_dec_set_global_model() local
580 struct hantro_dev *vpu = ctx->dev; in rockchip_vpu981_av1_dec_set_tile_info() local
686 struct hantro_dev *vpu = ctx->dev; in rockchip_vpu981_av1_dec_set_ref() local
759 struct hantro_dev *vpu = ctx->dev; in rockchip_vpu981_av1_dec_set_sign_bias() local
796 struct hantro_dev *vpu = ctx->dev; in rockchip_vpu981_av1_dec_set_segmentation() local
1072 struct hantro_dev *vpu = ctx->dev; in rockchip_vpu981_av1_dec_set_loopfilter() local
[all …]
A Dhantro_g2_hevc_dec.c13 struct hantro_dev *vpu = ctx->dev; in prepare_tile_info_buffer() local
147 struct hantro_dev *vpu = ctx->dev; in set_params() local
203 hantro_reg_write(vpu, &g2_sao_e, in set_params()
236 hantro_reg_write(vpu, &g2_idr_pic_e, in set_params()
242 hantro_reg_write(vpu, &g2_pcm_e, in set_params()
289 struct hantro_dev *vpu = ctx->dev; in set_ref_pic_list() local
371 struct hantro_dev *vpu = ctx->dev; in set_ref() local
506 struct hantro_dev *vpu = ctx->dev; in set_buffers() local
532 struct hantro_dev *vpu = ctx->dev; in prepare_scaling_list_buffer() local
582 struct hantro_dev *vpu = ctx->dev; in hantro_g2_hevc_dec_run() local
[all …]
A Dhantro_drv.c95 clk_bulk_disable(vpu->variant->num_clocks, vpu->clocks); in hantro_job_finish()
1047 if (!vpu) in hantro_probe()
1080 vpu->clocks[i].id = vpu->variant->clk_names[i]; in hantro_probe()
1107 vpu->reg_bases[i] = vpu->variant->reg_names ? in hantro_probe()
1113 vpu->enc_base = vpu->reg_bases[0] + vpu->variant->enc_offset; in hantro_probe()
1114 vpu->dec_base = vpu->reg_bases[0] + vpu->variant->dec_offset; in hantro_probe()
1151 dev_name(vpu->dev), vpu); in hantro_probe()
1160 ret = vpu->variant->init(vpu); in hantro_probe()
1197 vpu->mdev.dev = vpu->dev; in hantro_probe()
1201 vpu->v4l2_dev.mdev = &vpu->mdev; in hantro_probe()
[all …]
A Dhantro_postproc.c19 hantro_reg_write(vpu, \
26 hantro_reg_write_relaxed(vpu, \
71 struct hantro_dev *vpu = ctx->dev; in hantro_postproc_g1_enable() local
122 struct hantro_dev *vpu = ctx->dev; in hantro_postproc_g2_enable() local
183 struct hantro_dev *vpu = ctx->dev; in hantro_postproc_free() local
226 struct hantro_dev *vpu = ctx->dev; in hantro_postproc_alloc() local
271 struct hantro_dev *vpu = ctx->dev; in hantro_postproc_get_dec_buf_addr() local
296 struct hantro_dev *vpu = ctx->dev; in hantro_postproc_g1_disable() local
312 if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->disable) in hantro_postproc_disable()
320 if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->enable) in hantro_postproc_enable()
[all …]
A Drockchip_vpu2_hw_vp8_dec.c280 struct hantro_dev *vpu = ctx->dev; in cfg_lf() local
306 hantro_reg_write(vpu, &vp8_dec_mb_adj[i], in cfg_lf()
308 hantro_reg_write(vpu, &vp8_dec_ref_adj[i], in cfg_lf()
319 struct hantro_dev *vpu = ctx->dev; in cfg_qp() local
333 hantro_reg_write(vpu, &vp8_dec_quant[i], in cfg_qp()
347 struct hantro_dev *vpu = ctx->dev; in cfg_parts() local
430 struct hantro_dev *vpu = ctx->dev; in cfg_tap() local
439 hantro_reg_write(vpu, in cfg_tap()
450 struct hantro_dev *vpu = ctx->dev; in cfg_ref() local
487 struct hantro_dev *vpu = ctx->dev; in cfg_buffers() local
[all …]
A Drockchip_vpu2_hw_jpeg_enc.c51 vepu_write_relaxed(vpu, reg, VEPU_REG_INPUT_LUMA_INFO); in rockchip_vpu2_set_src_img_ctrl()
64 vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_CTRL1); in rockchip_vpu2_set_src_img_ctrl()
106 rockchip_vpu2_jpeg_enc_set_qtable(struct hantro_dev *vpu, in rockchip_vpu2_jpeg_enc_set_qtable() argument
123 vepu_write_relaxed(vpu, reg, VEPU_REG_JPEG_LUMA_QUAT(i)); in rockchip_vpu2_jpeg_enc_set_qtable()
134 struct hantro_dev *vpu = ctx->dev; in rockchip_vpu2_jpeg_enc_run() local
155 vepu_write_relaxed(vpu, VEPU_REG_ENCODE_FORMAT_JPEG, in rockchip_vpu2_jpeg_enc_run()
158 rockchip_vpu2_set_src_img_ctrl(vpu, ctx); in rockchip_vpu2_jpeg_enc_run()
171 vepu_write(vpu, reg, VEPU_REG_DATA_ENDIAN); in rockchip_vpu2_jpeg_enc_run()
174 vepu_write_relaxed(vpu, reg, VEPU_REG_AXI_CTRL); in rockchip_vpu2_jpeg_enc_run()
184 vepu_write(vpu, reg, VEPU_REG_ENCODE_START); in rockchip_vpu2_jpeg_enc_run()
[all …]
A Dhantro_g1_vp8_dec.c139 struct hantro_dev *vpu = ctx->dev; in cfg_lf() local
181 struct hantro_dev *vpu = ctx->dev; in cfg_qp() local
195 hantro_reg_write(vpu, &vp8_dec_quant[i], in cfg_qp()
234 struct hantro_dev *vpu = ctx->dev; in cfg_parts() local
282 hantro_reg_write(vpu, &reg, mb_size + 1); in cfg_parts()
306 vdpu_write_relaxed(vpu, in cfg_parts()
332 struct hantro_dev *vpu = ctx->dev; in cfg_tap() local
365 hantro_reg_write(vpu, &reg, val); in cfg_tap()
373 struct hantro_dev *vpu = ctx->dev; in cfg_ref() local
411 struct hantro_dev *vpu = ctx->dev; in cfg_buffers() local
[all …]
A Dhantro_h1_jpeg_enc.c18 static void hantro_h1_set_src_img_ctrl(struct hantro_dev *vpu, in hantro_h1_set_src_img_ctrl() argument
37 vepu_write_relaxed(vpu, reg, H1_REG_IN_IMG_CTRL); in hantro_h1_set_src_img_ctrl()
58 vepu_write_relaxed(vpu, size_left, H1_REG_STR_BUF_LIMIT); in hantro_h1_jpeg_enc_set_buffers()
63 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0); in hantro_h1_jpeg_enc_set_buffers()
80 hantro_h1_jpeg_enc_set_qtable(struct hantro_dev *vpu, in hantro_h1_jpeg_enc_set_qtable() argument
108 struct hantro_dev *vpu = ctx->dev; in hantro_h1_jpeg_enc_run() local
126 vepu_write_relaxed(vpu, H1_REG_ENC_CTRL_ENC_MODE_JPEG, in hantro_h1_jpeg_enc_run()
129 hantro_h1_set_src_img_ctrl(vpu, ctx); in hantro_h1_jpeg_enc_run()
143 vepu_write(vpu, reg, H1_REG_AXI_CTRL); in hantro_h1_jpeg_enc_run()
153 vepu_write(vpu, reg, H1_REG_ENC_CTRL); in hantro_h1_jpeg_enc_run()
[all …]
A Dimx8m_vpu_hw.c33 val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
58 ret = clk_bulk_prepare_enable(vpu->variant->num_clocks, vpu->clocks); in imx8mq_runtime_resume()
64 imx8m_soft_reset(vpu, RESET_G1 | RESET_G2); in imx8mq_runtime_resume()
65 imx8m_clk_enable(vpu, CLOCK_G1 | CLOCK_G2); in imx8mq_runtime_resume()
72 clk_bulk_disable_unprepare(vpu->variant->num_clocks, vpu->clocks); in imx8mq_runtime_resume()
239 struct hantro_dev *vpu = dev_id; in imx8m_vpu_g1_irq() local
247 vdpu_write(vpu, 0, G1_REG_INTERRUPT); in imx8m_vpu_g1_irq()
250 hantro_irq_done(vpu, state); in imx8m_vpu_g1_irq()
257 vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1]; in imx8mq_vpu_hw_init()
264 struct hantro_dev *vpu = ctx->dev; in imx8m_vpu_g1_reset() local
[all …]
A Dhantro_g1_h264_dec.c28 struct hantro_dev *vpu = ctx->dev; in set_params() local
49 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0); in set_params()
55 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1); in set_params()
65 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2); in set_params()
71 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL3); in set_params()
110 vdpu_write_relaxed(vpu, 0, G1_REG_ERR_CONC); in set_params()
113 vdpu_write_relaxed(vpu, in set_params()
130 struct hantro_dev *vpu = ctx->dev; in set_ref() local
209 struct hantro_dev *vpu = ctx->dev; in set_buffers() local
252 struct hantro_dev *vpu = ctx->dev; in hantro_g1_h264_dec_run() local
[all …]
A Drockchip_vpu2_hw_mpeg2_dec.c153 struct hantro_dev *vpu = ctx->dev; in rockchip_vpu2_mpeg2_dec_run() local
173 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50)); in rockchip_vpu2_mpeg2_dec_run()
177 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51)); in rockchip_vpu2_mpeg2_dec_run()
182 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52)); in rockchip_vpu2_mpeg2_dec_run()
185 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53)); in rockchip_vpu2_mpeg2_dec_run()
193 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54)); in rockchip_vpu2_mpeg2_dec_run()
199 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56)); in rockchip_vpu2_mpeg2_dec_run()
211 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57)); in rockchip_vpu2_mpeg2_dec_run()
217 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(120)); in rockchip_vpu2_mpeg2_dec_run()
225 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(122)); in rockchip_vpu2_mpeg2_dec_run()
[all …]
A Drockchip_vpu2_hw_h264_dec.c199 struct hantro_dev *vpu = ctx->dev; in set_params() local
207 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50)); in set_params()
211 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51)); in set_params()
216 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52)); in set_params()
219 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53)); in set_params()
227 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54)); in set_params()
233 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56)); in set_params()
302 struct hantro_dev *vpu = ctx->dev; in set_ref() local
426 struct hantro_dev *vpu = ctx->dev; in set_buffers() local
469 struct hantro_dev *vpu = ctx->dev; in rockchip_vpu2_h264_dec_run() local
[all …]
A Drockchip_vpu_hw.c371 struct hantro_dev *vpu = dev_id; in rockchip_vpu1_vepu_irq() local
382 hantro_irq_done(vpu, state); in rockchip_vpu1_vepu_irq()
389 struct hantro_dev *vpu = dev_id; in rockchip_vpu2_vdpu_irq() local
400 hantro_irq_done(vpu, state); in rockchip_vpu2_vdpu_irq()
407 struct hantro_dev *vpu = dev_id; in rockchip_vpu2_vepu_irq() local
418 hantro_irq_done(vpu, state); in rockchip_vpu2_vepu_irq()
425 struct hantro_dev *vpu = dev_id; in rk3588_vpu981_irq() local
436 hantro_irq_done(vpu, state); in rk3588_vpu981_irq()
465 struct hantro_dev *vpu = ctx->dev; in rk3066_vpu_dec_reset() local
473 struct hantro_dev *vpu = ctx->dev; in rockchip_vpu1_enc_reset() local
[all …]
A Dhantro_g1_mpeg2_dec.c111 vdpu_write_relaxed(vpu, addr, G1_REG_RLC_VLC_BASE); in hantro_g1_mpeg2_dec_set_buffers()
150 struct hantro_dev *vpu = ctx->dev; in hantro_g1_mpeg2_dec_run() local
181 vdpu_write_relaxed(vpu, reg, G1_SWREG(2)); in hantro_g1_mpeg2_dec_run()
194 vdpu_write_relaxed(vpu, reg, G1_SWREG(3)); in hantro_g1_mpeg2_dec_run()
200 vdpu_write_relaxed(vpu, reg, G1_SWREG(4)); in hantro_g1_mpeg2_dec_run()
208 vdpu_write_relaxed(vpu, reg, G1_SWREG(5)); in hantro_g1_mpeg2_dec_run()
212 vdpu_write_relaxed(vpu, reg, G1_SWREG(6)); in hantro_g1_mpeg2_dec_run()
221 vdpu_write_relaxed(vpu, reg, G1_SWREG(18)); in hantro_g1_mpeg2_dec_run()
225 vdpu_write_relaxed(vpu, reg, G1_SWREG(48)); in hantro_g1_mpeg2_dec_run()
228 vdpu_write_relaxed(vpu, reg, G1_SWREG(55)); in hantro_g1_mpeg2_dec_run()
[all …]
A Dhantro.h93 int (*init)(struct hantro_dev *vpu);
94 int (*runtime_resume)(struct hantro_dev *vpu);
395 writel_relaxed(val, vpu->enc_base + reg); in vepu_write_relaxed()
401 writel(val, vpu->enc_base + reg); in vepu_write()
406 u32 val = readl(vpu->enc_base + reg); in vepu_read()
416 writel_relaxed(val, vpu->dec_base + reg); in vdpu_write_relaxed()
422 writel(val, vpu->dec_base + reg); in vdpu_write()
434 u32 val = readl(vpu->dec_base + reg); in vdpu_read()
446 v = vdpu_read(vpu, reg->base); in vdpu_read_mask()
456 vdpu_write(vpu, vdpu_read_mask(vpu, reg, val), reg->base); in hantro_reg_write()
[all …]
A Dhantro_g1.c16 struct hantro_dev *vpu = dev_id; in hantro_g1_irq() local
20 status = vdpu_read(vpu, G1_REG_INTERRUPT); in hantro_g1_irq()
24 vdpu_write(vpu, 0, G1_REG_INTERRUPT); in hantro_g1_irq()
25 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in hantro_g1_irq()
27 hantro_irq_done(vpu, state); in hantro_g1_irq()
34 struct hantro_dev *vpu = ctx->dev; in hantro_g1_reset() local
36 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT); in hantro_g1_reset()
37 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in hantro_g1_reset()
38 vdpu_write(vpu, 1, G1_REG_SOFT_RESET); in hantro_g1_reset()
/drivers/remoteproc/
A Dingenic_rproc.c61 struct vpu { struct
71 struct vpu *vpu = rproc->priv; in ingenic_rproc_prepare() argument
75 ret = clk_bulk_prepare_enable(ARRAY_SIZE(vpu->clks), vpu->clks); in ingenic_rproc_prepare()
84 struct vpu *vpu = rproc->priv; in ingenic_rproc_unprepare() local
86 clk_bulk_disable_unprepare(ARRAY_SIZE(vpu->clks), vpu->clks); in ingenic_rproc_unprepare()
93 struct vpu *vpu = rproc->priv; in ingenic_rproc_start() local
107 struct vpu *vpu = rproc->priv; in ingenic_rproc_stop() local
119 struct vpu *vpu = rproc->priv; in ingenic_rproc_kick() local
126 struct vpu *vpu = rproc->priv; in ingenic_rproc_da_to_va() local
155 struct vpu *vpu = rproc->priv; in vpu_interrupt() local
[all …]
/drivers/media/platform/mediatek/mdp/
A Dmtk_mdp_vpu.c15 return container_of(vpu, struct mtk_mdp_ctx, vpu); in vpu_to_ctx()
26 vpu->inst_addr = msg->vpu_inst_addr; in mtk_mdp_vpu_handle_init_ack()
38 vpu->failure = msg->status; in mtk_mdp_vpu_ipi_handler()
39 if (!vpu->failure) { in mtk_mdp_vpu_ipi_handler()
48 ctx = vpu_to_ctx(vpu); in mtk_mdp_vpu_ipi_handler()
55 ctx = vpu_to_ctx(vpu); in mtk_mdp_vpu_ipi_handler()
57 msg_id, vpu->failure); in mtk_mdp_vpu_ipi_handler()
81 if (!vpu->pdev) { in mtk_mdp_vpu_send_msg()
104 msg.ap_inst = (unsigned long)vpu; in mtk_mdp_vpu_send_ap_ipi()
106 if (!err && vpu->failure) in mtk_mdp_vpu_send_ap_ipi()
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