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Searched refs:vsync_source (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_top.c123 if (cfg->vsync_source >= DPU_VSYNC_SOURCE_WD_TIMER_4 && in dpu_hw_setup_wd_timer()
124 cfg->vsync_source <= DPU_VSYNC_SOURCE_WD_TIMER_0) { in dpu_hw_setup_wd_timer()
125 switch (cfg->vsync_source) { in dpu_hw_setup_wd_timer()
188 reg |= (cfg->vsync_source & 0xf) << pp_offset[pp_idx]; in dpu_hw_setup_vsync_sel()
A Ddpu_hw_top.h67 enum dpu_vsync_source vsync_source; member
A Ddpu_encoder.h38 enum dpu_vsync_source vsync_source; member
A Ddpu_hw_intf.h110 void (*vsync_sel)(struct dpu_hw_intf *intf, enum dpu_vsync_source vsync_source);
A Ddpu_hw_intf.c478 enum dpu_vsync_source vsync_source) in dpu_hw_intf_vsync_sel() argument
487 DPU_REG_WRITE(c, INTF_TEAR_MDP_VSYNC_SEL, (vsync_source & 0xf)); in dpu_hw_intf_vsync_sel()
A Ddpu_kms.c562 info->vsync_source = DPU_VSYNC_SOURCE_GPIO_0; in dpu_kms_dsi_set_te_source()
570 info->vsync_source = i; in dpu_kms_dsi_set_te_source()
A Ddpu_encoder.c792 vsync_cfg.vsync_source = disp_info->vsync_source; in _dpu_encoder_update_vsync_source()
801 vsync_cfg.vsync_source); in _dpu_encoder_update_vsync_source()

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