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Searched refs:vsync_start (Results 1 – 25 of 217) sorted by relevance

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/drivers/gpu/drm/panel/
A Dpanel-simple.c805 .vsync_start = 800 + 3,
831 .vsync_start = 272 + 2,
855 .vsync_start = 480 + 2,
1122 .vsync_start = 600 + 1,
1231 .vsync_start = 768 + 4,
1503 .vsync_start = 800 + 8,
1631 .vsync_start = 272 + 8,
1788 .vsync_start = 768 + 4,
1973 .vsync_start = 240 + 4,
1998 .vsync_start = 240 + 4,
[all …]
A Dpanel-edp.c1021 .vsync_start = 768 + 10,
1034 .vsync_start = 768 + 4,
1089 .vsync_start = 768 + 3,
1112 .vsync_start = 800 + 3,
1123 .vsync_start = 800 + 3,
1196 .vsync_start = 1080 + 3,
1266 .vsync_start = 768 + 8,
1328 .vsync_start = 1080 + 4,
1350 .vsync_start = 1440 + 3,
1377 .vsync_start = 768 + 5,
[all …]
A Dpanel-arm-versatile.c143 .vsync_start = 240 + 5,
166 .vsync_start = 480 + 11,
188 .vsync_start = 220 + 0,
211 .vsync_start = 320 + 2,
A Dpanel-tpo-tpg110.c111 .vsync_start = 480 + 10,
127 .vsync_start = 480 + 18,
143 .vsync_start = 272 + 2,
159 .vsync_start = 640 + 4,
175 .vsync_start = 240 + 2,
A Dpanel-ilitek-ili9322.c543 .vsync_start = 240 + 4,
556 .vsync_start = 240 + 21,
570 .vsync_start = 240 + 4,
584 .vsync_start = 320 + 4,
597 .vsync_start = 360 + 4,
611 .vsync_start = 480 + 4,
625 .vsync_start = 480 + 4,
A Dpanel-newvision-nv3052c.c833 .vsync_start = 480 + 5,
845 .vsync_start = 480 + 5,
860 .vsync_start = 480 + 12,
875 .vsync_start = 480 + 21,
A Dpanel-sitronix-st7703.c140 .vsync_start = 1440 + 20,
319 .vsync_start = 1440 + 18,
406 .vsync_start = 480 + 18,
490 .vsync_start = 720 + 15,
576 .vsync_start = 1280 + 16,
658 .vsync_start = 480 + 17,
A Dpanel-novatek-nt35560.c67 .vsync_start = 864 + 14,
86 .vsync_start = 864 + 1,
109 .vsync_start = 854 + 14,
128 .vsync_start = 854 + 1,
A Dpanel-himax-hx8394.c187 .vsync_start = 1440 + 9,
316 .vsync_start = 1280 + 12,
463 .vsync_start = 1280 + 13,
604 .vsync_start = 1920 + 16,
A Dpanel-newvision-nv3051d.c442 .vsync_start = 480 + 18,
454 .vsync_start = 480 + 18,
466 .vsync_start = 480 + 18,
481 .vsync_start = 480 + 18,
A Dpanel-leadtek-ltk050h3146w.c305 .vsync_start = 1280 + 9,
386 .vsync_start = 1280 + 12,
445 .vsync_start = 1280 + 18,
/drivers/gpu/drm/gud/
A Dgud_internal.h140 dst->vsync_start = cpu_to_le16(src->vsync_start); in gud_from_display_mode()
158 dst->vsync_start = le16_to_cpu(src->vsync_start); in gud_to_display_mode()
/drivers/gpu/drm/msm/dp/
A Ddp_panel.c312 display_v_start = ((drm_mode->vtotal - drm_mode->vsync_start) * in msm_dp_panel_tpg_enable()
314 display_v_end = ((vsync_period - (drm_mode->vsync_start - in msm_dp_panel_tpg_enable()
325 v_sync_width = drm_mode->vsync_end - drm_mode->vsync_start; in msm_dp_panel_tpg_enable()
556 drm_mode->vsync_start - drm_mode->vdisplay, in msm_dp_panel_timing_cfg()
557 drm_mode->vsync_end - drm_mode->vsync_start); in msm_dp_panel_timing_cfg()
569 data = (drm_mode->vtotal - drm_mode->vsync_start); in msm_dp_panel_timing_cfg()
575 data = drm_mode->vsync_end - drm_mode->vsync_start; in msm_dp_panel_timing_cfg()
636 drm_mode->vsync_start - drm_mode->vdisplay, in msm_dp_panel_init_panel_info()
637 drm_mode->vsync_end - drm_mode->vsync_start); in msm_dp_panel_init_panel_info()
/drivers/gpu/drm/
A Ddrm_modes.c505 mode->vsync_start = mode->vdisplay + vfp; in fill_analog_mode()
506 mode->vsync_end = mode->vsync_start + vslen; in fill_analog_mode()
768 drm_mode->vsync_end = drm_mode->vsync_start + vsync; in drm_cvt_mode()
800 drm_mode->vsync_end = drm_mode->vsync_start + vsync; in drm_cvt_mode()
1081 dmode->vsync_end = dmode->vsync_start + vm->vsync_len; in drm_display_mode_from_videomode()
1360 p->crtc_vsync_start = p->vsync_start; in drm_mode_set_crtcinfo()
1481 mode1->vsync_start == mode2->vsync_start && in drm_mode_match_timings()
1650 mode->vsync_start < mode->vdisplay || in drm_mode_validate_basic()
1651 mode->vsync_end < mode->vsync_start || in drm_mode_validate_basic()
2592 out->vsync_start = in->vsync_start; in drm_mode_convert_to_umode()
[all …]
/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_encoders.c172 unsigned int vover = native_mode->vsync_start - native_mode->vdisplay; in amdgpu_panel_mode_fixup()
174 unsigned int vsync_width = native_mode->vsync_end - native_mode->vsync_start; in amdgpu_panel_mode_fixup()
187 adjusted_mode->vsync_start = native_mode->vdisplay + vover; in amdgpu_panel_mode_fixup()
188 adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width; in amdgpu_panel_mode_fixup()
/drivers/gpu/drm/msm/disp/mdp4/
A Dmdp4_dsi_encoder.c55 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal; in mdp4_dsi_encoder_mode_set()
56 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dsi_hsync_skew; in mdp4_dsi_encoder_mode_set()
57 …display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dsi_hsync_s… in mdp4_dsi_encoder_mode_set()
A Dmdp4_dtv_encoder.c59 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal; in mdp4_dtv_encoder_mode_set()
60 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew; in mdp4_dtv_encoder_mode_set()
61 …display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_s… in mdp4_dtv_encoder_mode_set()
/drivers/gpu/drm/imx/dcss/
A Ddcss-ss.c125 u16 vsync_start, vsync_end; in dcss_ss_sync_set() local
144 vsync_start = vm->vfront_porch - 1; in dcss_ss_sync_set()
148 ((u32)vsync_end << SYNC_END_POS) | vsync_start, in dcss_ss_sync_set()
/drivers/gpu/drm/radeon/
A Dradeon_encoders.c330 unsigned int vover = native_mode->vsync_start - native_mode->vdisplay; in radeon_panel_mode_fixup()
332 unsigned int vsync_width = native_mode->vsync_end - native_mode->vsync_start; in radeon_panel_mode_fixup()
347 adjusted_mode->vsync_start = native_mode->vdisplay + vover; in radeon_panel_mode_fixup()
348 adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width; in radeon_panel_mode_fixup()
/drivers/gpu/drm/hisilicon/hibmc/dp/
A Ddp_hw.c90 vstart = mode->vtotal - mode->vsync_start; in hibmc_dp_link_cfg()
103 mode->vsync_start - mode->vdisplay); in hibmc_dp_link_cfg()
119 mode->vsync_start - mode->vdisplay); in hibmc_dp_link_cfg()
122 mode->vsync_end - mode->vsync_start); in hibmc_dp_link_cfg()
/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_encoder_phys_vid.c53 || (mode->vsync_start < mode->vdisplay) in drm_mode_to_intf_timing_params()
55 || (mode->vsync_end < mode->vsync_start)) { in drm_mode_to_intf_timing_params()
61 mode->vsync_start, mode->vsync_end, in drm_mode_to_intf_timing_params()
82 timing->v_front_porch = mode->vsync_start - mode->vdisplay; in drm_mode_to_intf_timing_params()
84 timing->vsync_pulse_width = mode->vsync_end - mode->vsync_start; in drm_mode_to_intf_timing_params()
728 fetch_start = mode.vtotal - (mode.vsync_start - mode.vdisplay); in dpu_encoder_phys_vid_get_frame_count()
/drivers/gpu/drm/i915/display/
A Dintel_vrr_regs.h106 #define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start)) argument
/drivers/gpu/drm/sti/
A Dsti_vtg.c218 fallsync_top += mode->vsync_end - mode->vsync_start; in vtg_set_hsync_vsync_pos()
224 fallsync_top = mode->vsync_end - mode->vsync_start; in vtg_set_hsync_vsync_pos()
317 u32 start_line = mode.vtotal - mode.vsync_start + 1; in sti_vtg_get_line_number()
/drivers/gpu/drm/msm/disp/mdp5/
A Dmdp5_encoder.c77 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal; in mdp5_vid_encoder_mode_set()
78 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew; in mdp5_vid_encoder_mode_set()
79 …display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_s… in mdp5_vid_encoder_mode_set()
/drivers/gpu/drm/bridge/adv7511/
A Dadv7533.c37 vsw = mode->vsync_end - mode->vsync_start; in adv7533_dsi_config_timing_gen()
38 vfp = mode->vsync_start - mode->vdisplay; in adv7533_dsi_config_timing_gen()

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