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Searched refs:vtaps (Results 1 – 25 of 26) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
A Ddcn10_dpp_dscl.c450 bool dpp1_dscl_is_lb_conf_valid(int ceil_vratio, int num_partitions, int vtaps) in dpp1_dscl_is_lb_conf_valid() argument
453 return vtaps <= (num_partitions - ceil_vratio + 2); in dpp1_dscl_is_lb_conf_valid()
455 return vtaps <= num_partitions; in dpp1_dscl_is_lb_conf_valid()
463 int vtaps = scl_data->taps.v_taps; in dpp1_dscl_find_lb_memory_config() local
478 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) in dpp1_dscl_find_lb_memory_config()
485 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) in dpp1_dscl_find_lb_memory_config()
494 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) in dpp1_dscl_find_lb_memory_config()
503 ASSERT(dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) in dpp1_dscl_find_lb_memory_config()
A Ddcn10_dpp.h1400 int vtaps);
/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
A Ddcn401_dpp_dscl.c466 static bool dpp401_dscl_is_lb_conf_valid(int ceil_vratio, int num_partitions, int vtaps) in dpp401_dscl_is_lb_conf_valid() argument
469 return vtaps <= (num_partitions - ceil_vratio + 2); in dpp401_dscl_is_lb_conf_valid()
471 return vtaps <= num_partitions; in dpp401_dscl_is_lb_conf_valid()
479 int vtaps = scl_data->taps.v_taps; in dpp401_dscl_find_lb_memory_config() local
494 if (dpp401_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) in dpp401_dscl_find_lb_memory_config()
501 if (dpp401_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) in dpp401_dscl_find_lb_memory_config()
510 if (dpp401_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) in dpp401_dscl_find_lb_memory_config()
519 ASSERT(dpp401_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) in dpp401_dscl_find_lb_memory_config()
/drivers/gpu/drm/amd/display/dc/dml/dcn21/
A Ddisplay_mode_vba_21.c163 double vtaps,
321 unsigned int vtaps[],
1211 double vtaps, in CalculatePrefetchSourceLines() argument
1864 mode_lib->vba.vtaps[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2450 mode_lib->vba.vtaps, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3541 } else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0 in dml21_ModeSupportAndSystemConfigurationFull()
4026 / (mode_lib->vba.vtaps[k] in dml21_ModeSupportAndSystemConfigurationFull()
4692 mode_lib->vba.vtaps[k], in dml21_ModeSupportAndSystemConfigurationFull()
5020 mode_lib->vba.vtaps, in dml21_ModeSupportAndSystemConfigurationFull()
5275 unsigned int vtaps[], in CalculateWatermarksAndDRAMSpeedChangeSupport()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calc_auto.c99 v->vtaps[k] = v->override_vta_ps[k]; in scaler_settings_calculation()
102 v->vtaps[k] = v->acceptable_quality_vta_ps; in scaler_settings_calculation()
331 …v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max3(v->vtaps[k] / 6.0 *dcn_bw_min2(… in mode_support_and_system_configuration()
427 …v->number_of_dpp_required_for_lb_size =dcn_bw_ceil2((v->vtaps[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ra… in mode_support_and_system_configuration()
554 …(v->swath_width_yper_state[i][j][k] /dcn_bw_max2(v->h_ratio[k], 1.0)), 1.0)) - (v->vtaps[k] - 1.0); in mode_support_and_system_configuration()
747 …v->v_init_y = (v->v_ratio[k] + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k]) /… in mode_support_and_system_configuration()
759 …v->v_init_c = (v->v_ratio[k] / 2.0 + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio… in mode_support_and_system_configuration()
1190 …v->dppclk_using_single_dpp_luma = v->pixel_clock[k] *dcn_bw_max3(v->vtaps[k] / 6.0 *dcn_bw_min2(1.… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1596 …v->v_init_pre_fill_y[k] =dcn_bw_floor2((v->v_ratio[k] + v->vtaps[k] + 1.0 + v->interlace_output[k]… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1607 …v->v_init_pre_fill_c[k] =dcn_bw_floor2((v->v_ratio[k] / 2.0 + v->vtaps[k] + 1.0 + v->interlace_out… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
[all …]
A Ddcn_calcs.c404 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps; in pipe_ctx_to_e2e_pipe_params()
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddisplay_mode_vba_20.c125 double vtaps,
812 double vtaps, in CalculatePrefetchSourceLines() argument
1133 mode_lib->vba.vtaps[k] / 6.0 in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1893 mode_lib->vba.vtaps[k], in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3305 || mode_lib->vba.vtaps[k] != 1.0)) { in dml20_ModeSupportAndSystemConfigurationFull()
3307 } else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0 in dml20_ModeSupportAndSystemConfigurationFull()
3685 mode_lib->vba.vtaps[k] / 6.0 in dml20_ModeSupportAndSystemConfigurationFull()
3719 mode_lib->vba.vtaps[k] / 6.0 in dml20_ModeSupportAndSystemConfigurationFull()
3830 / (mode_lib->vba.vtaps[k] in dml20_ModeSupportAndSystemConfigurationFull()
3845 / (mode_lib->vba.vtaps[k] in dml20_ModeSupportAndSystemConfigurationFull()
[all …]
A Ddisplay_mode_vba_20v2.c149 double vtaps,
872 double vtaps, in CalculatePrefetchSourceLines() argument
1193 mode_lib->vba.vtaps[k] / 6.0 in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1929 mode_lib->vba.vtaps[k], in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3412 || mode_lib->vba.vtaps[k] != 1.0)) { in dml20v2_ModeSupportAndSystemConfigurationFull()
3414 } else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0 in dml20v2_ModeSupportAndSystemConfigurationFull()
3792 mode_lib->vba.vtaps[k] / 6.0 in dml20v2_ModeSupportAndSystemConfigurationFull()
3826 mode_lib->vba.vtaps[k] / 6.0 in dml20v2_ModeSupportAndSystemConfigurationFull()
3937 / (mode_lib->vba.vtaps[k] in dml20v2_ModeSupportAndSystemConfigurationFull()
3952 / (mode_lib->vba.vtaps[k] in dml20v2_ModeSupportAndSystemConfigurationFull()
[all …]
A Ddcn20_fpu.c1577 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1; in dcn20_populate_dml_pipes_from_context()
1683 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps; in dcn20_populate_dml_pipes_from_context()
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddisplay_mode_vba_30.c174 double vtaps,
329 unsigned int vtaps[],
1611 double vtaps, in CalculatePrefetchSourceLines() argument
2280 v->vtaps[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2765 v->vtaps, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3568 || v->vtaps[k] != 1.0)) { in dml30_ModeSupportAndSystemConfigurationFull()
3570 } else if (v->vtaps[k] < 1.0 || v->vtaps[k] > 8.0 in dml30_ModeSupportAndSystemConfigurationFull()
3577 || v->VRatio[k] > v->vtaps[k] in dml30_ModeSupportAndSystemConfigurationFull()
4456 v->vtaps[k], in dml30_ModeSupportAndSystemConfigurationFull()
5042 v->vtaps, in dml30_ModeSupportAndSystemConfigurationFull()
[all …]
/drivers/gpu/drm/amd/amdgpu/
A Ddce_v8_0.c661 u32 vtaps; /* vertical scaler taps */ member
864 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v8_0_latency_watermark()
865 (wm->vtaps >= 5) || in dce_v8_0_latency_watermark()
954 if (lb_partitions <= (wm->vtaps + 1)) in dce_v8_0_check_latency_hiding()
1016 wm_high.vtaps = 1; in dce_v8_0_program_watermarks()
1018 wm_high.vtaps = 2; in dce_v8_0_program_watermarks()
1055 wm_low.vtaps = 1; in dce_v8_0_program_watermarks()
1057 wm_low.vtaps = 2; in dce_v8_0_program_watermarks()
A Ddce_v6_0.c561 u32 vtaps; /* vertical scaler taps */ member
764 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v6_0_latency_watermark()
765 (wm->vtaps >= 5) || in dce_v6_0_latency_watermark()
854 if (lb_partitions <= (wm->vtaps + 1)) in dce_v6_0_check_latency_hiding()
925 wm_high.vtaps = 1; in dce_v6_0_program_watermarks()
927 wm_high.vtaps = 2; in dce_v6_0_program_watermarks()
952 wm_low.vtaps = 1; in dce_v6_0_program_watermarks()
954 wm_low.vtaps = 2; in dce_v6_0_program_watermarks()
A Ddce_v10_0.c708 u32 vtaps; /* vertical scaler taps */ member
911 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v10_0_latency_watermark()
912 (wm->vtaps >= 5) || in dce_v10_0_latency_watermark()
1001 if (lb_partitions <= (wm->vtaps + 1)) in dce_v10_0_check_latency_hiding()
1063 wm_high.vtaps = 1; in dce_v10_0_program_watermarks()
1065 wm_high.vtaps = 2; in dce_v10_0_program_watermarks()
1102 wm_low.vtaps = 1; in dce_v10_0_program_watermarks()
1104 wm_low.vtaps = 2; in dce_v10_0_program_watermarks()
A Ddce_v11_0.c740 u32 vtaps; /* vertical scaler taps */ member
943 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v11_0_latency_watermark()
944 (wm->vtaps >= 5) || in dce_v11_0_latency_watermark()
1033 if (lb_partitions <= (wm->vtaps + 1)) in dce_v11_0_check_latency_hiding()
1095 wm_high.vtaps = 1; in dce_v11_0_program_watermarks()
1097 wm_high.vtaps = 2; in dce_v11_0_program_watermarks()
1134 wm_low.vtaps = 1; in dce_v11_0_program_watermarks()
1136 wm_low.vtaps = 2; in dce_v11_0_program_watermarks()
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddisplay_mode_vba_31.c191 double vtaps,
1736 double vtaps, argument
1777 dml_print("DML::%s: vtaps = %f\n", __func__, vtaps);
2051 v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
2411 v->vtaps[k],
3817 || v->VRatio[k] != 1.0 || v->vtaps[k] != 1.0)) {
3819 } else if (v->vtaps[k] < 1.0 || v->vtaps[k] > 8.0 || v->htaps[k] < 1.0 || v->htaps[k] > 8.0
3822 || v->VRatio[k] > v->vtaps[k]
3960 v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
3976 v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn314/
A Ddisplay_mode_vba_314.c200 double vtaps,
1753 double vtaps, argument
1794 dml_print("DML::%s: vtaps = %f\n", __func__, vtaps);
2069 v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
2430 v->vtaps[k],
3910 || v->VRatio[k] != 1.0 || v->vtaps[k] != 1.0)) {
3912 } else if (v->vtaps[k] < 1.0 || v->vtaps[k] > 8.0 || v->htaps[k] < 1.0 || v->htaps[k] > 8.0
3915 || v->VRatio[k] > v->vtaps[k]
4051 v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
4067 v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
[all …]
/drivers/gpu/drm/amd/display/dc/dml/
A Ddisplay_mode_lib.c259 dml_print("DML PARAMS: vtaps = %d\n", scale_taps->vtaps); in dml_log_pipe_params()
A Ddisplay_mode_structs.h502 unsigned int vtaps; member
A Ddisplay_mode_vba.c600 mode_lib->vba.vtaps[mode_lib->vba.NumberOfActivePlanes] = taps->vtaps; in fetch_pipe_params()
A Ddisplay_mode_vba.h468 unsigned int vtaps[DC__NUM_DPP__MAX]; member
/drivers/gpu/drm/radeon/
A Devergreen.c1947 u32 vtaps; /* vertical scaler taps */ member
2084 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in evergreen_latency_watermark()
2085 (wm->vtaps >= 5) || in evergreen_latency_watermark()
2141 if (lb_partitions <= (wm->vtaps + 1)) in evergreen_check_latency_hiding()
2201 wm_high.vtaps = 1; in evergreen_program_watermarks()
2203 wm_high.vtaps = 2; in evergreen_program_watermarks()
2228 wm_low.vtaps = 1; in evergreen_program_watermarks()
2230 wm_low.vtaps = 2; in evergreen_program_watermarks()
A Dsi.c2046 u32 vtaps; /* vertical scaler taps */ member
2201 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce6_latency_watermark()
2202 (wm->vtaps >= 5) || in dce6_latency_watermark()
2260 if (lb_partitions <= (wm->vtaps + 1)) in dce6_check_latency_hiding()
2323 wm_high.vtaps = 1; in dce6_program_watermarks()
2325 wm_high.vtaps = 2; in dce6_program_watermarks()
2350 wm_low.vtaps = 1; in dce6_program_watermarks()
2352 wm_low.vtaps = 2; in dce6_program_watermarks()
A Dcik.c8929 u32 vtaps; /* vertical scaler taps */ member
9132 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce8_latency_watermark()
9133 (wm->vtaps >= 5) || in dce8_latency_watermark()
9222 if (lb_partitions <= (wm->vtaps + 1)) in dce8_check_latency_hiding()
9285 wm_high.vtaps = 1; in dce8_program_watermarks()
9287 wm_high.vtaps = 2; in dce8_program_watermarks()
9325 wm_low.vtaps = 1; in dce8_program_watermarks()
9327 wm_low.vtaps = 2; in dce8_program_watermarks()
/drivers/gpu/drm/amd/display/dc/inc/
A Ddcn_calcs.h203 float vtaps[number_of_planes_minus_one + 1]; member
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddisplay_mode_vba_32.c127 mode_lib->vba.vtaps[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
447 …hParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VTaps = mode_lib->vba.vtaps[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1758 || mode_lib->vba.VRatio[k] != 1.0 || mode_lib->vba.vtaps[k] != 1.0)) { in dml32_ModeSupportAndSystemConfigurationFull()
1760 …} else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0 || mode_lib->vba.htaps[k] … in dml32_ModeSupportAndSystemConfigurationFull()
1766 || mode_lib->vba.VRatio[k] > mode_lib->vba.vtaps[k] in dml32_ModeSupportAndSystemConfigurationFull()
1906 mode_lib->vba.htaps[k], mode_lib->vba.HTAPsChroma[k], mode_lib->vba.vtaps[k], in dml32_ModeSupportAndSystemConfigurationFull()
1940 / (mode_lib->vba.vtaps[k] + dml_max(dml_ceil(mode_lib->vba.VRatio[k], 1.0) - 2, 0.0)); in dml32_ModeSupportAndSystemConfigurationFull()
2741 …_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VTaps = mode_lib->vba.vtaps[k]; in dml32_ModeSupportAndSystemConfigurationFull()

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