Searched refs:width_in_mb (Results 1 – 2 of 2) sorted by relevance
630 unsigned int width_in_mb = width / 16; in amdgpu_uvd_cs_msg_decode() local632 unsigned int fs_in_mb = width_in_mb * height_in_mb; in amdgpu_uvd_cs_msg_decode()680 min_dpb_size += width_in_mb * height_in_mb * 32; in amdgpu_uvd_cs_msg_decode()689 min_dpb_size += width_in_mb * height_in_mb * 128; in amdgpu_uvd_cs_msg_decode()692 min_dpb_size += width_in_mb * 64; in amdgpu_uvd_cs_msg_decode()695 min_dpb_size += width_in_mb * 128; in amdgpu_uvd_cs_msg_decode()698 tmp = max(width_in_mb, height_in_mb); in amdgpu_uvd_cs_msg_decode()714 min_dpb_size += width_in_mb * height_in_mb * 64; in amdgpu_uvd_cs_msg_decode()757 width_in_mb * height_in_mb * num_dpb_buffer * 192; in amdgpu_uvd_cs_msg_decode()760 min_dpb_size += width_in_mb * height_in_mb * 32; in amdgpu_uvd_cs_msg_decode()[all …]
363 unsigned width_in_mb = width / 16; in radeon_uvd_cs_msg_decode() local379 min_dpb_size += width_in_mb * height_in_mb * 17 * 192; in radeon_uvd_cs_msg_decode()382 min_dpb_size += width_in_mb * height_in_mb * 32; in radeon_uvd_cs_msg_decode()391 min_dpb_size += width_in_mb * height_in_mb * 128; in radeon_uvd_cs_msg_decode()394 min_dpb_size += width_in_mb * 64; in radeon_uvd_cs_msg_decode()397 min_dpb_size += width_in_mb * 128; in radeon_uvd_cs_msg_decode()400 tmp = max(width_in_mb, height_in_mb); in radeon_uvd_cs_msg_decode()416 min_dpb_size += width_in_mb * height_in_mb * 64; in radeon_uvd_cs_msg_decode()419 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); in radeon_uvd_cs_msg_decode()
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