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Searched refs:wm_table (Results 1 – 21 of 21) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddcn30_fpu.c294 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) { in dcn30_fpu_update_soc_for_wm_a()
361 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { in dcn30_fpu_calculate_wm_and_dlg()
408 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { in dcn30_fpu_calculate_wm_and_dlg()
669 base->bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn3_fpu_build_wm_range_table()
674 base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0; in dcn3_fpu_build_wm_range_table()
691 base->bw_params->wm_table.nv_entries[WM_C].valid = true; in dcn3_fpu_build_wm_range_table()
692 base->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 0; in dcn3_fpu_build_wm_range_table()
696 base->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = 0; in dcn3_fpu_build_wm_range_table()
710 base->bw_params->wm_table.nv_entries[WM_D].valid = true; in dcn3_fpu_build_wm_range_table()
712 base->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = 2; in dcn3_fpu_build_wm_range_table()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
A Drn_clk_mgr.h33 extern struct wm_table ddr4_wm_table_gs;
34 extern struct wm_table lpddr4_wm_table_gs;
35 extern struct wm_table lpddr4_wm_table_with_disabled_ppt;
36 extern struct wm_table ddr4_wm_table_rn;
37 extern struct wm_table ddr4_1R_wm_table_rn;
38 extern struct wm_table lpddr4_wm_table_rn;
A Drn_clk_mgr.c462 if (!bw_params->wm_table.entries[i].valid) in build_watermark_ranges()
679 bw_params->wm_table.entries[i].wm_inst = i; in rn_clk_mgr_helper_populate_bw_params()
682 bw_params->wm_table.entries[i].valid = false; in rn_clk_mgr_helper_populate_bw_params()
686 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in rn_clk_mgr_helper_populate_bw_params()
687 bw_params->wm_table.entries[i].valid = true; in rn_clk_mgr_helper_populate_bw_params()
745 rn_bw_params.wm_table = lpddr4_wm_table_with_disabled_ppt; in rn_clk_mgr_construct()
748 rn_bw_params.wm_table = lpddr4_wm_table_gs; in rn_clk_mgr_construct()
750 rn_bw_params.wm_table = lpddr4_wm_table_rn; in rn_clk_mgr_construct()
754 rn_bw_params.wm_table = ddr4_wm_table_gs; in rn_clk_mgr_construct()
757 rn_bw_params.wm_table = ddr4_1R_wm_table_rn; in rn_clk_mgr_construct()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
A Ddcn316_clk_mgr.c270 static struct wm_table ddr4_wm_table = {
307 static struct wm_table lpddr5_wm_table = {
356 if (!bw_params->wm_table.entries[i].valid) in dcn316_build_watermark_ranges()
359 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn316_build_watermark_ranges()
360 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn316_build_watermark_ranges()
553 bw_params->wm_table.entries[i].wm_inst = i; in dcn316_clk_mgr_helper_populate_bw_params()
556 bw_params->wm_table.entries[i].valid = false; in dcn316_clk_mgr_helper_populate_bw_params()
560 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in dcn316_clk_mgr_helper_populate_bw_params()
561 bw_params->wm_table.entries[i].valid = true; in dcn316_clk_mgr_helper_populate_bw_params()
640 dcn316_bw_params.wm_table = lpddr5_wm_table; in dcn316_clk_mgr_construct()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c211 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn32_build_wm_range_table_fpu()
220 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; in dcn32_build_wm_range_table_fpu()
223 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true; in dcn32_build_wm_range_table_fpu()
231 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF; in dcn32_build_wm_range_table_fpu()
236 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true; in dcn32_build_wm_range_table_fpu()
237 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 50; in dcn32_build_wm_range_table_fpu()
257 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true; in dcn32_build_wm_range_table_fpu()
266 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF; in dcn32_build_wm_range_table_fpu()
2439 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { in dcn32_calculate_wm_and_dlg_fpu()
2508 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { in dcn32_calculate_wm_and_dlg_fpu()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
A Ddcn315_clk_mgr.c305 static struct wm_table ddr5_wm_table = {
342 static struct wm_table lpddr5_wm_table = {
391 if (!bw_params->wm_table.entries[i].valid) in dcn315_build_watermark_ranges()
394 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn315_build_watermark_ranges()
395 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn315_build_watermark_ranges()
574 bw_params->wm_table.entries[i].wm_inst = i; in dcn315_clk_mgr_helper_populate_bw_params()
577 bw_params->wm_table.entries[i].valid = false; in dcn315_clk_mgr_helper_populate_bw_params()
581 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in dcn315_clk_mgr_helper_populate_bw_params()
582 bw_params->wm_table.entries[i].valid = true; in dcn315_clk_mgr_helper_populate_bw_params()
657 dcn315_bw_params.wm_table = lpddr5_wm_table; in dcn315_clk_mgr_construct()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
A Ddcn31_clk_mgr.c344 static struct wm_table ddr5_wm_table = {
381 static struct wm_table lpddr5_wm_table = {
430 if (!bw_params->wm_table.entries[i].valid) in dcn31_build_watermark_ranges()
433 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn31_build_watermark_ranges()
434 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn31_build_watermark_ranges()
621 bw_params->wm_table.entries[i].wm_inst = i; in dcn31_clk_mgr_helper_populate_bw_params()
624 bw_params->wm_table.entries[i].valid = false; in dcn31_clk_mgr_helper_populate_bw_params()
628 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in dcn31_clk_mgr_helper_populate_bw_params()
629 bw_params->wm_table.entries[i].valid = true; in dcn31_clk_mgr_helper_populate_bw_params()
729 dcn31_bw_params.wm_table = lpddr5_wm_table; in dcn31_clk_mgr_construct()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
A Dvg_clk_mgr.h32 extern struct wm_table ddr4_wm_table;
33 extern struct wm_table lpddr5_wm_table;
A Dvg_clk_mgr.c394 if (!bw_params->wm_table.entries[i].valid) in vg_build_watermark_ranges()
397 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in vg_build_watermark_ranges()
398 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in vg_build_watermark_ranges()
604 bw_params->wm_table.entries[i].wm_inst = i; in vg_clk_mgr_helper_populate_bw_params()
607 bw_params->wm_table.entries[i].valid = false; in vg_clk_mgr_helper_populate_bw_params()
611 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in vg_clk_mgr_helper_populate_bw_params()
612 bw_params->wm_table.entries[i].valid = true; in vg_clk_mgr_helper_populate_bw_params()
721 vg_bw_params.wm_table = lpddr5_wm_table; in vg_clk_mgr_construct()
723 vg_bw_params.wm_table = ddr4_wm_table; in vg_clk_mgr_construct()
/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.c218 struct wm_table ddr4_wm_table = {
255 struct wm_table lpddr5_wm_table = {
429 table_entry = &bw_params->wm_table.entries[WM_D]; in dcn301_fpu_calculate_wm_and_dlg()
437 table_entry = &bw_params->wm_table.entries[WM_C]; in dcn301_fpu_calculate_wm_and_dlg()
442 table_entry = &bw_params->wm_table.entries[WM_B]; in dcn301_fpu_calculate_wm_and_dlg()
448 table_entry = &bw_params->wm_table.entries[WM_A]; in dcn301_fpu_calculate_wm_and_dlg()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
A Ddcn314_clk_mgr.c403 static struct wm_table ddr5_wm_table = {
440 static struct wm_table lpddr5_wm_table = {
494 if (!bw_params->wm_table.entries[i].valid) in dcn314_build_watermark_ranges()
497 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn314_build_watermark_ranges()
498 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn314_build_watermark_ranges()
742 bw_params->wm_table.entries[i].wm_inst = i; in dcn314_clk_mgr_helper_populate_bw_params()
745 bw_params->wm_table.entries[i].valid = false; in dcn314_clk_mgr_helper_populate_bw_params()
749 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in dcn314_clk_mgr_helper_populate_bw_params()
750 bw_params->wm_table.entries[i].valid = true; in dcn314_clk_mgr_helper_populate_bw_params()
839 dcn314_bw_params.wm_table = lpddr5_wm_table; in dcn314_clk_mgr_construct()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
A Ddcn401_clk_mgr.c189 clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn401_build_wm_range_table()
192 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; in dcn401_build_wm_range_table()
193 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; in dcn401_build_wm_range_table()
194 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; in dcn401_build_wm_range_table()
197 clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid = false; in dcn401_build_wm_range_table()
202 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = true; in dcn401_build_wm_range_table()
205 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_dcfclk = 0xFFFF; in dcn401_build_wm_range_table()
207 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_uclk = 0xFFFF; in dcn401_build_wm_range_table()
209 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = false; in dcn401_build_wm_range_table()
213 clk_mgr->bw_params->wm_table.nv_entries[WM_1B].valid = false; in dcn401_build_wm_range_table()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
A Ddcn30_clk_mgr.c341 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) { in dcn3_notify_wm_ranges()
342 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()
343 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()
344 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinUclk = clk_mgr->base.bw_params->wm_table.nv_entri… in dcn3_notify_wm_ranges()
345 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxUclk = clk_mgr->base.bw_params->wm_table.nv_entri… in dcn3_notify_wm_ranges()
347 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries… in dcn3_notify_wm_ranges()
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddcn31_fpu.c458 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn31_update_soc_for_wm_a()
459 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()
460 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A… in dcn31_update_soc_for_wm_a()
461 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_t… in dcn31_update_soc_for_wm_a()
469 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn315_update_soc_for_wm_a()
474 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn315_update_soc_for_wm_a()
476 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us; in dcn315_update_soc_for_wm_a()
478 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us; in dcn315_update_soc_for_wm_a()
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dclk_mgr.h247 struct wm_table { struct
267 struct wm_table wm_table; argument
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
A Ddcn35_clk_mgr.c646 static struct wm_table ddr5_wm_table = {
683 static struct wm_table lpddr5_wm_table = {
755 if (!bw_params->wm_table.entries[i].valid) in dcn35_build_watermark_ranges()
758 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn35_build_watermark_ranges()
759 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn35_build_watermark_ranges()
1061 bw_params->wm_table.entries[i].wm_inst = i; in dcn35_clk_mgr_helper_populate_bw_params()
1064 bw_params->wm_table.entries[i].valid = false; in dcn35_clk_mgr_helper_populate_bw_params()
1068 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in dcn35_clk_mgr_helper_populate_bw_params()
1069 bw_params->wm_table.entries[i].valid = true; in dcn35_clk_mgr_helper_populate_bw_params()
1321 dcn35_bw_params.wm_table = lpddr5_wm_table; in dcn35_clk_mgr_construct()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddcn20_fpu.c768 struct wm_table ddr4_wm_table_gs = {
805 struct wm_table lpddr4_wm_table_gs = {
879 struct wm_table ddr4_wm_table_rn = {
916 struct wm_table ddr4_1R_wm_table_rn = {
953 struct wm_table lpddr4_wm_table_rn = {
2295 table_entry = &bw_params->wm_table.entries[WM_D]; in dcn21_calculate_wm()
2303 table_entry = &bw_params->wm_table.entries[WM_C]; in dcn21_calculate_wm()
2308 table_entry = &bw_params->wm_table.entries[WM_B]; in dcn21_calculate_wm()
2314 table_entry = &bw_params->wm_table.entries[WM_A]; in dcn21_calculate_wm()
2470 bw_params->wm_table.entries[WM_D].wm_inst = WM_D; in dcn21_clk_mgr_set_bw_params_wm_table()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
A Ddcn32_clk_mgr.c984 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) { in dcn32_notify_wm_ranges()
986 …table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_bre… in dcn32_notify_wm_ranges()
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dvega12_hwmgr.c2563 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega12_display_configuration_changed_task() local
2568 (uint8_t *)wm_table, TABLE_WATERMARKS, false); in vega12_display_configuration_changed_task()
A Dvega20_hwmgr.c3656 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega20_display_configuration_changed_task() local
3661 (uint8_t *)wm_table, TABLE_WATERMARKS, false); in vega20_display_configuration_changed_task()
A Dvega10_hwmgr.c4971 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega10_display_configuration_changed_task() local
4976 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false); in vega10_display_configuration_changed_task()

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